Command latency circuit for programmable SLDRAM and latency...

Details Command latency circuit for programmable SLDRAM and latency... Command latency circuit for programmable SLDRAM and latency...

1999-12-29

2001-04-10

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S240000, C365S194000, C365S233100, C365S189020, C365S230020, C365S189120

Reexamination Certificate

active

06215722

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a command latency circuit for a programmable SynchLink Dynamic Random Access Memory (hereinafter, referred to as ‘SLDRAM’) which is an ultrahigh speed memory device, and a latency control method therefor.
2. Description of the Background Art
As the high integration of a semiconductor memory device has been rapidly achieved, the ultrahigh speed thereof has also proceeded. Especially, the SLDRAM achieving the ultrahigh speed has been recently developed.
The SLDRAM is a kind of Dynamic Random Access Memory (hereinafter, referred to as ‘DRAM’), and has a ultrahigh speed performance superior to a conventional synchronous DRAM. Especially, the SLDRAM is operated at a rising edge and a falling edge of a clock, and thus has a considerably high data bandwidth. Firstly, command signals (namely, /RAS, /CAS, /WE, etc.) and address signals which are necessary to perform a DRAM operation are inputted to the SLDRAM as a single packet four times, having a total width of 40 bits, through pins of 10 bits which are command addresses. The SLDRAM carries out the general DRAM operations (read, write, etc.) and the other specific operations by decoding the command address of 40 bits. The SLDRAM performs a bank read/write operation and a page read/write operation, and is operated at burst
4
or burst
8
. In addition, during the read/write operation, the SLDRAM can adjust a time of transmitting/receiving a data to/from a controller by using an internally-stored register value. The register value can be programmed to have an appropriate value by the controller.
On the other hand, the conventional SLDRAM utilizes a master clock in a write command latency. Accordingly, there is not provided a specific logic structure for controlling the bank write operation. As a result, a write command latency circuit is operated in other operations, besides the bank write operation (for example, read latency), thereby increasing the power consumption. In addition, loading of the master clock is remarkably increased. Furthermore, many shift registers are required to delay a write command, and thus disadvantageously occupy a large area in the device.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a command latency circuit for a programmable SynchLink Dynamic Random Access Memory (SLDRAM) which can reduce the power consumption by decreasing loading of a master clock, and a latency control method therefor.
It is another object of the present invention to provide a command latency circuit for a programmable SLDRAM which can perform a delay program by using a register, and reduce the number of shift registers for delaying a write command, and a latency control method therefor.
In order to achieve the above-described objects of the present invention, there is provided a command latency circuit for a programmable SLDRAM, including: a command decoder unit for decoding and outputting an input of a command address; an internal clock generating unit for outputting an internal clock according to an input of a master clock while a latency is operated; a register decoder unit for receiving and decoding a register data; a burst control unit for receiving the output signal from the command decoder unit and the internal clock, and outputting a command pulse; a shift register unit for shift-outputting the output signal from the burst control unit according to an input of the internal clock; and an output unit for receiving the output signals from the shift register unit and the register decoder unit, and outputting a command signal having a wanted delay.
In addition, there is provided a command latency control method for a programmable SLDRAM, including: a step for decoding and outputting an input of a command address; a step for generating an internal clock by synchronizing the decoded command wit h a master clock; a step for synchronizing the command with the internal clock, and outputting it after a predetermined delay time; a step for selecting the delayed command according to a register data ; and a step for outputting the selected command after a predetermined latency according to the register data.


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