Command generating circuit and semiconductor memory device...

Details Command generating circuit and semiconductor memory device... Command generating circuit and semiconductor memory device...

2007-01-09

2009-02-17

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C365S230080, C365S233190

Reexamination Certificate

active

07492661

ABSTRACT:
In a command generating circuit, operation mode signals (signals determining internal operations, such as ACTIVE, READ, WRITE, and PRECHARGE) are determined by decoding command signals /CS, /RAS, /CAS, and /WE. The operation mode signals and bank select signals (BS0, BS1, BS2, and BS3) are latched by internal clocks. Thereafter, a logical product (AND) of each of the latched operation mode signals and each of the latched bank select signals is calculated.

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patent: 8-124380 (1996-05-01), None
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patent: 2002-025254 (2002-01-01), None

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