Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2003-05-27
2004-02-17
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S201000
Reexamination Certificate
active
06693846
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a circuit configuration having a flow controller that can be put into a plurality of states and which outputs a respective command, in a respective one of the states, to a circuit component to be controlled. The flow controller has at least one asynchronously operating delay circuit via which the flow controller moves from one of the states into the respective next state. The invention also relates to an integrated memory and to a test configuration having such a circuit configuration.
Integrated memories, for example in the form of DRAMs (Dynamic Random Access Memories), are operated in data processing systems and in this case are actuated by a microprocessor or memory controller, for example. From a certain size of the memory device upward, for example for a memory size of over 1 Mbit, all available DRAMs normally use a so-called “multiplex address scheme.” Such a multiplex address scheme has the advantage that it is very well suited to the functionality of a DRAM.
In general, for memory access, first the word lines which are to be addressed and then the bit lines which are to be selected are activated in synchronicity with a clock signal. The address scheme thus involves row addresses being transmitted first and then corresponding column addresses. This selects those memory cells from which data are read and those memory cells to which data are written. Similarly, the microprocessor or memory controller transmits a plurality of single commands, for read access particularly in the form of a word line activation signal, a column access signal and, to complete memory access, a word line deactivation signal.
One drawback of such a functionality is, in particular, that a DRAM interface used for the purpose is not immediately aligned with a corresponding processor interface which communicates with fast “SRAM” memories. In contrast to DRAMs, SRAMs are very much smaller and faster and they are generally not operated in a multiplex address scheme as described. However, SRAMs have the drawback that they are considerably more expensive than DRAMs.
Efforts are therefore generally made to use DRAMs also for applications in which SRAM memories have been used previously. In order to be able to use a DRAM also instead of an SRAM, access commands are combined into a macro command which is then processed within one clock cycle. When the macro command has been applied, the single commands for controlling access in a flow controller which can be put into a plurality of states are generated out of sync with the clock signal, with a respective single command being output to the access controller in a respective one of the states. The duration of the individual commands is set using asynchronously operating delay circuits via which the flow controller moves from one of the states into the respective next state. This allows a DRAM to be actuated with a command set that is oriented to fast SRAM memories.
To establish the operational functionality or serviceability of an integrated memory, a memory that is to be checked is operated in a test configuration in which a test unit is connected to the memory, and the functionality of the memory is checked. Particularly for the purpose of checking the command sequence for memory access, it is advantageous and appropriate if the single commands run in sync with a clock, since normal test units operate in sync with a clock.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration of the above-mentioned type which overcomes the disadvantages of the heretofore-known devices and methods of this general type and in which, in a test mode of the circuit configuration, for example, the commands are output in synchronized fashion.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, comprising:
a flow controller enabled to assume a plurality of states and for outputting a respective command, in each of the states, to a circuit component to be controlled;
the flow controller having at least one asynchronously operating delay circuit, the flow controller moving from one state into a respectively next state via the delay circuit;
a further signal path connected in parallel with the delay circuit, the further signal path having a clock-controlled multivibrator; and
a switch connected to alternatively operate the delay circuit and the further signal path.
In accordance with the invention, the delay circuit in the flow controller mentioned initially has a further signal path connected in parallel with it which has a clock-controlled multivibrator. In the novel circuit, the delay circuit and the further signal path can be operated alternatively using a switch. This allows, for example in a test mode of the circuit configuration, the commands output by the flow controller to be output by the flow controller in synchronized fashion. The invention then affords the advantage that the basically asynchronously operating flow controller, which thereby controls the command sequence, particularly in a normal mode, does not need to be modified. In addition, the additional circuit complexity is kept comparatively low by virtue of the provision of the multivibrator.
The invention can be used, in principle, in any type of circuit configuration which has a flow controller which can be put into a plurality of states and which outputs a respective command, in a respective one of the states, to a circuit component which is to be controlled. The invention thus allows the command sequence from a flow controller which operates asynchronously per se to be synchronized with a clock in a second operating state.
With the above and other objects in view there is also provided, in accordance with the invention, an integrated memory device that comprises a plurality of memory cells, an access controller for controlling an access to the memory cells, and a circuit configuration as outlined above. The flow controller is connected to output the commands to the access controller for controlling the access to the memory cells.
In other words, the invention can be used with particular advantage in an integrated memory in which a flow controller is connected, for the purpose of outputting commands, to an access controller for controlling access to memory cells in the memory. Such a memory is suitable, particularly in a normal mode, for controlling memory access using a command sequence oriented to fast SRAM memories, as described in more detail in the introduction. In addition, however, a memory in accordance with the invention allows, particularly for the purpose of testing the memory using a test unit operating in sync with a clock signal, the command sequence for memory access to be synchronized with the clock signal and hence to be rendered checkable by the test unit.
In accordance with an advantageous embodiment of the invention, the clock-controlled multivibrator is in the form of a clock-controlled D-type flip-flop circuit. The delay circuit has an input and an output, with an inverter chain being connected between the input and the output in one embodiment of the delay circuit. The further signal path is connected in parallel with the inverter chain between the input and the output. Alternatively, the delay circuit can have another configuration. It generally outputs the input signal at the output, delayed by a particular time.
With the above and other objects in view there is therefore provided, in accordance with the invention, a test configuration that comprises the above-outlined circuit configuration and a test unit connected to the circuit configuration. The further signal path is thereby connected via the switch, and the multivibrator is actuated by a clock signal of the test unit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration having
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tran Andrew Q.
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