Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-05-06
2008-05-06
Le, Thong Q. (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185290, C365S189040, C365S189090
Reexamination Certificate
active
07369438
ABSTRACT:
A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that each array may be addressed with common addressing signals. The combination volatile and nonvolatile memory integrated circuit further has a memory control circuit in communication with external circuitry to receive address, command, and data signals. The memory control circuit interprets the address, command, and data signals, and for transfer to the volatile memory array and the nonvolatile memory arrays for reading, writing, programming, and erasing the volatile and nonvolatile memory arrays. The volatile memory array is may be a SRAM, a pseudo SRAM, or a DRAM. Any of the nonvolatile memory arrays maybe masked programmed ROM arrays, NAND configured flash memory NAND configured EEPROM.
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Co-pending U.S. App. No. 11/025,822, filed Dec. 24, 2004, “A Novel Combination Nonvolatile Integrated Memory System Using a Universal Technology Most Suitable for High Density, High-Flexibility and High-Security Sim-Card, Smart-Card and E-Passport Applications”, assigned to the same assignee as the present invention.
Co-pending U.S. App. No. 10/351,180, filed Jan. 24, 2003, A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page and Block Write with No Disturb and Divided-Well in the Cell Array Using a Unified Cell Structure and Technology with a New Scheme of Decoder and Layout, assigned to the same assignee as the present invention.
Ackerman Stephen B.
Aplus Flash Technology Inc.
Knowles Billy
Le Thong Q.
Saile Ackerman LLC
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