Combining switch for reducing accesses to memory and for synchro

Details Combining switch for reducing accesses to memory and for synchro Combining switch for reducing accesses to memory and for synchro

1988-11-02

1992-11-10

Lee, Thomas C.

Boots, shoes, and leggings

3642281, 3642293, 3642306, 3642707, 364DIG2, 395550, G06F 13372

Patent

active

051631490

ABSTRACT:
A combining switch that reduces memory accesses, synchronizes parallel processors and is easy to implement, is achieved by configuring a plurality of parallel processing nodes in a ring arrangement and by implementing a synchronizing instruction for the switch that facilitates, rather than inhibits, parallel processing. According to the preferred embodiment of the invention the ring is a token ring and the synchronizing instruction is a Fetch-and-Add instruction.

REFERENCES:
patent: 4404557 (1983-09-01), Grow
patent: 4495617 (1985-01-01), Ampulski
patent: 4512014 (1985-04-01), Binz
patent: 4530091 (1985-07-01), Crockett
patent: 4536876 (1985-08-01), Bahr
patent: 4539679 (1985-09-01), Bux et al.
patent: 4543630 (1985-09-01), Neches et al.
patent: 4549291 (1985-10-01), Renoulin
patent: 4604742 (1986-08-01), Hamada
patent: 4609920 (1986-09-01), Segarra
patent: 4663748 (1987-05-01), Karbowiak
patent: 4677614 (1987-06-01), Circo
patent: 4680757 (1987-07-01), Murakami
patent: 4704680 (1987-11-01), Saxe
patent: 4709364 (1987-11-01), Hasegawa
patent: 4713807 (1987-12-01), Caves
patent: 4746920 (1988-05-01), Nellen
patent: 4747130 (1988-05-01), Ho
patent: 4754395 (1988-06-01), Weisshaar
patent: 4771423 (1988-09-01), Ohya
patent: 4805167 (1989-02-01), Leslie
patent: 4814762 (1989-03-01), Franaszek
patent: 4815110 (1989-03-01), Benson
patent: 4833468 (1989-05-01), Larson et al.
patent: 4847754 (1989-07-01), Obermarck
patent: 4926446 (1990-05-01), Grover
patent: 4930121 (1990-05-01), Shiobara
patent: 4989131 (1991-01-01), Stone
The NYU Ultra Computer-Designing an MIMO Shared Memory Parallel Computer, by A. Gottlieb et al., IEEE transactions on computers vol. C-32, Feb. 1983, pp. 175-189.
Shift arithmetic on a token ring network, by M. Livny and U. Manber IEEE, 1985 pp. 301-304.
The IBM Research Parallel Processor Prototype (RP3) Introduction and Architecture, by G. F. Pfister et al., 1985, IEEE, pp. 764-771.

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