Combined write-operand queue and read-after-write dependency sco

Details Combined write-operand queue and read-after-write dependency sco Combined write-operand queue and read-after-write dependency sco

1992-10-30

1995-11-28

Eng, David Y.

Boots, shoes, and leggings

3642318, 364933, 3649483, G06F 9312

Patent

active

054715911

ABSTRACT:
In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in a source queue and a destination queue. An execution unit successively obtains source specifiers of an instruction from the source queue, initiates an operation upon the source specifiers, reads a destination specifier from the destination queue, and retires the result at the specified destination. Read-after-write conflicts may occur because the execution unit may overlap execution of a plurality of instructions. Just prior to beginning execution of a current instruction, the destination queue is checked for conflict between the source specifiers of the current instruction and the destination specifiers of previously issued but not yet retired instructions. When an instruction is issued for execution, its destination specifiers in the destination queue are marked to indicate that they are associated with an executed but not yet retired instruction. In a preferred construction, each entry of the queue has a "write pending" bit that is cleared during a flush and when a read pointer is incremented. An issue pointer identifies the entry of an instruction next to be issued, so that the write-pending bit is set when the issue pointer is incremented. Each entry has two comparators enabled by the write-pending bit to detect a conflict with two source specifiers.

REFERENCES:
patent: Re32493 (1987-09-01), Matsumoto et al.
patent: 4789925 (1988-12-01), Lahti
patent: 4875160 (1989-10-01), Brown, III
patent: 4891753 (1990-01-01), Budde et al.
patent: 5067069 (1991-11-01), Fite et al.
patent: 5068781 (1991-11-01), Gillett
patent: 5109495 (1992-04-01), Fite et al.
patent: 5125083 (1992-06-01), Fite
patent: 5142631 (1992-08-01), Murray et al.
patent: 5142633 (1992-08-01), Murray et al.
patent: 5214768 (1993-05-01), Martia
patent: 5251306 (1993-10-01), Tran
Acosta et al., "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors," IEEE Transactions in Computers C-35 (Sep. 1986) No. 9, New York, N.Y., pp. 815-828.
Matsumoto et al., "A High-Performance Architecture for Variable Length Instructions", Systems & Computers in Japan, No. 3 (May 1985), Washington, D.C., pp. 19-28.
Fossum et al., "New VAX Squeezes Mainframe Power Into Mini Package", Computer Design, vol. 24, No. 3 (Mar. 1985), Littleton, Mass., pp. 173-181.

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