Combined trench isolation and inlaid process for integrated circ

Details Combined trench isolation and inlaid process for integrated circ Combined trench isolation and inlaid process for integrated circ

1997-09-17

1999-10-05

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438221, 257330, H01L 2176

Patent

active

059638184

ABSTRACT:
A method for forming an integrated circuit involves forming trench isolation regions (208a) and a damascene gate electrode region (214) simultaneous with one another via overlapping process steps. By performing this simultaneous formation of a trench region (208a) and a damascene gate electrode (214) using a common dielectric layer (208), MOS integrated circuits can be formed with reduced processing steps while simultaneously avoiding adverse polysilicon stringers which are present in prior art damacene-formed gate electrode. A single dielectric layer (208) is deposited in order to provide trench fill material for a trench region (208a) while simultaneously providing the material needed for form an opening (210) which is used to define the dimensions and material content of a gate electrode (214).

REFERENCES:
patent: 5434093 (1995-07-01), Chau et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5795811 (1998-08-01), Kim et al.
patent: 5866465 (1999-02-01), Doan et al.

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