Combined synchronous and asynchronous memory controller

Details Combined synchronous and asynchronous memory controller Combined synchronous and asynchronous memory controller

1989-11-03

1993-06-08

Bowler, Alyssa H.

Boots, shoes, and leggings

364DIG1, 364240, 3642405, 3642403, 395500, G06F 1320, G06F 1336, G06F 1338

Patent

active

052186865

ABSTRACT:
A memory controller has an asynchronous portion and a synchronous portion. The synchronous portion is used when the system processor is accessing the memory, while the asynchronous portion is used when control of the memories is held by a DMA controller or a bus master located on a standardized bus.

REFERENCES:
patent: 3999163 (1976-12-01), Levy et al.
patent: 4292669 (1981-09-01), Wollum et al.
patent: 4615017 (1986-09-01), Finlay et al.
patent: 4937777 (1990-06-01), Flood et al.
C. H. Chan, et al., A CMOS Multi-Mode Data Acquisition System Implemented Using a Workstation Based VLS1 Design Environment, IEEE, Electronicom '85, Oct. 6-11, 1985, pp. 28-31.
IBM Technical Disclosure Bull., Direct, Asynchronous and Synchronous Storage Card, vol. 29, No. 4, Sep. 1986, pp. 1452-1456.

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