Combined single-ended and differential signaling interface

Details Combined single-ended and differential signaling interface Combined single-ended and differential signaling interface

1999-04-29

2004-12-28

Vu, Ngoc-Yen (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

C326S081000, C327S052000, C375S219000, C375S316000

Reexamination Certificate

active

06836290

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of interface circuits, and more particularly, to interface circuitry for providing selectable single-ended and differential signal output from a CMOS image sensor to an external digital signal processor.
2. Description of Related Art
One of the advantages of CMOS image sensors (CMOS imagers) over CCD imagers is that the CMOS imager chip can include digital signal processing circuitry. In practice, the signal processing is more often performed on a companion chip, in order to provide greater application flexibility. However, CMOS imagers often have integrated analog to digital converters to convert the analog signal to a digital bit stream that can be processed by the companion chip. The digitized information then must be transferred to companion chip or other external devices for picture storage, processing, or transmission. A single-ended interface is the most common and simplest implementation for data transfer. An example of a single-ended interface is shown in
FIG. 1. A
driver circuit
2
in the CMOS imager
1
outputs a signal to the companion processing chip
3
. A receiver
4
receives and amplifies the signal for further processing.
FIG. 2
is a schematic of one possible CMOS implementation of the above-described single-ended interface.
A differential interface can minimize power and noise generation as compared to a single-ended interface, but generally requires twice the number of signal lines. An example of conventional low voltage differential signaling (LVDS) circuit
11
is shown in FIG.
3
. The LVDS
11
circuit includes a current source I
1
(nominal 3.5 mA) which drives one of the differential pair lines
13
,
15
. The receiver
17
has a high DC impedance (it does not source or sink DC current), so the majority of driver current flows across the 100 &OHgr; termination resistor R
1
generating about 350 mV across the receiver inputs
19
,
21
. When the driver
23
switches, it changes the direction of current flow across the resistor R
1
, thereby creating a valid “one” or “zero” logic state.
LVDS technology saves power in several important ways. The power dissipated by the load (the 100 &OHgr; termination resistor R
1
is a mere 1.2 mW. In comparison, an RS
422
driver typically delivers 3 volts across a 100 &OHgr; termination, for 90 mW power consumption—75 times more than LVDS. Similarly, LVDS devices
11
require roughly one-tenth the power supply current of PECL/ECL devices.
Aside from the power dissipated in the load and static I
CC
current, LVDS also lowers system power requirements through its CMOS current-mode driver design. This design greatly reduces the frequency component of I
CC
. The I
CC
vs. Frequency plot for LVDS
11
is virtually flat between 10 MHz and 100 MHz for the quad devices (<50 mA total for driver+receiver at 100 MHz). In contrast, single-ended, TTL/CMOS transceivers exhibit dynamic power consumption which increases exponentially with frequency.
To help ensure reliability, LVDS receivers
17
have a fail-safe feature that guarantees the output to be in a known logic state (HIGH) under certain fault conditions. These conditions include open, shorted, or terminated receiver inputs. If the driver
23
loses power, is disabled or is removed from the line, while the receiver
17
stays powered on with inputs terminated, the receiver output remains in a known state with the fail-safe feature.
If LVDS receivers
17
did not have the fail-safe feature and one of the fault conditions occurred, any external noise above the receiver thresholds could trigger the output and cause an error. A receiver without fail-safe could even go into oscillation under certain fault conditions. The fail-safe features ensure that the receiver output will be a HIGH—rather than an unknown state—under fault conditions.
FIG. 4
illustrates CMOS video imaging sensing circuitry according to the preferred embodiment disclosed in co-pending U.S. application Ser. No 09/062,343. This circuitry includes a CMOS image sensor chip
50
and an image processor chip
52
. The CMOS image sensor chip
50
typically includes a number of light responsive CMOS pixel sensors which develop analog signals representative of an image. These analog signals are then A to D converted by the ADC circuit to form digital signals Din
0
, Din
1
. . . Din
n
. The image processor chip
52
includes a data processor
53
which performs various manipulations of the image data such as compression and color processing. The processor
53
may be software driven or a hardware embodiment.
As may be seen, the circuit of
FIG. 4
employs a plurality of LVDS circuits
11
. Each circuit
11
includes a respective driver
54
and a respective receiver
56
. Each driver
54
receives a respective input signal Din
0
, Din
1
. . . Din
n
, which are digital logic levels of, for example, 3.3 volts for logic “1” and zero volts for logic “
0
”. Changes in state in these signals are transmitted over the differential lines to the respective receivers
56
. Each receiver
56
generates a respective output signal Dout
0
, Dout
1
, . . . Dout
n
, which are at the several hundred milli-volt level.
It is possible to use a differential interface as shown in
FIG. 4
instead of a single-ended interface on the imager, but existing image processing devices may only support the common single-ended interface of FIG.
1
and not the differential interface. It is possible to place both interfaces on the imager in order to support both types of companion chips, but this would add pins and cost.
The best solution would be to implement an interface that could be selected to either support a single-ended interface or a differential interface using the same number of pins (i.e. without requiring twice the number of pins for the differential interface). This would allow flexibility in supporting both commonly available single-ended image processing devices and new image processing devices with the low noise differential interface.
Using a small number of digital data interface pins will minimize power, IC cost, package cost, and printed circuit board size. However, the data rate per pin is inversely proportional to the number of pins. Higher data rates will result in higher noise such as electromagnetic interference and chip output ground bounce. Also, if the number of digital data interface pins is less than the data word size, then some form of synchronization is often required, which can increase complexity and cost.
One tested imager device has a 4 bit single-ended pixel data interface. The data word size is 12 bits, so each pixel's data is transferred in three clocks, 4 bits at a time. Because multiple clock cycles are required to transfer each pixel data, synchronization codes are required so that the image processing device can tell whether a 4 bit transfer is the most significant, middle significant, or least significant 4 bits of the pixel data. This synchronization adds complexity and cost to the system.
As imagers are developed with greater resolution, the number of pixels per frame is much higher. In order to limit the per pin data rate to a reasonable speed, the interface was widened to the width of the 10 bit pixel data. However, the data rate is still high, and will result in fast signal transition times and in ground bounce. Both of these effects may couple noise into the imager silicon substrate, increasing the noise in the image.
A differential interface may be used, but usually this results in twice the number of pins, because two pins are used for each bit transfer, one for the “true” value (normal value) and another for the “complement” value. Thus, there is a need for an improved interface circuit that would allow either a single-ended or a differential output and using as few pins as possible.
SUMMARY OF THE INVENTION
The present invention is a data interface for CMOS imagers that can be either a single-ended interface or a differential interface. The single-ended interface provides c

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