Combined sense amplifier and latching circuit for high speed rom

Details Combined sense amplifier and latching circuit for high speed rom Combined sense amplifier and latching circuit for high speed rom

1991-10-04

1993-04-20

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307290, 307363, 307279, 307360, 3052722, 365205, 36518909, H03F 345, H03K 5153

Patent

active

052045609

ABSTRACT:
A combined sense amplifier and latching circuit receives an input signal (VIN) at an input terminal (22). A sense amplifier includes a gated-loop type master latch (ML) having two cascaded inverters (I12, I13) with a common node (I) coupled therebetween and a control device (TG4) in the master latch loop controlled by a gating signal (55A). A reference voltage generator generates a reference voltage (VREF). The two inverters are biased between a first supply voltage (Vdd) having a magnitude greater than the reference voltage and either a second supply voltage (GND) or the reference voltage depending on the value of the gating signal. The input terminal is connected to the input of one of the inverters. A gated-loop slave latch (SL) is connected in series with the sense amplifier and includes two cascaded inverters (I14, I15) with a common node (M) coupled therebetween and a control device (P15) in the slave latch loop controlled by the gating signal. The sense amplifier and the slave latch are isolated from each other by a control device (TG5) controlled by the gating signal.

REFERENCES:
patent: 3636527 (1972-01-01), Zuk
patent: 4804865 (1989-02-01), Clark, II
patent: 4837465 (1989-06-01), Rubinstein
patent: 4897568 (1990-01-01), Chern et al.
patent: 5003511 (1991-03-01), Secol et al.
patent: 5023480 (1991-06-01), Gieseke et al.
"Level-Sensitive Scan Design tests chips, boards, system" Berglund, Electronics/Mar. 15, 1979, pp. 108-110.
IBM Disc. Bul. vol. 17 No. 1, Jun. 1974, "Low-input impedance FET (or Bi-FET) sense amplifier" Cassidy et al.

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