Combined read/write cycle for a direct memory access controller

Details Combined read/write cycle for a direct memory access controller Combined read/write cycle for a direct memory access controller

1985-07-26

1988-01-26

Williams, Jr., Archie E.

Boots, shoes, and leggings

G06F 1328

Patent

active

047220511

ABSTRACT:
A data processing system has a plurality of peripheral devices and a main memory, a direct memory access controller for controlling the transfer of data between the main memory and the peripheral devices including a local memory connected to the peripheral devices for storing data written to and read from the peripheral devices, a sequencer for controlling the transfer of data between the main memory and the local memory, a local address register connected to the sequencer for providing the local memory address for memory operations of the local memory, a system address register connected to the sequencer for providing the main memory address for memory operations of the main memory, and a data register for holding data transferred between the main memory and the local memory. The sequencer includes a controller for generating control signals for the main memory, the local memory and the data register in control cycles to transfer a word of data between the main memory and the local memory in a single control cycle.

REFERENCES:
patent: 4479179 (1984-10-01), Dinwiddie
patent: 4481578 (1984-11-01), Hughes

Affiliated with

Also associated with

Rating

Combined read/write cycle for a direct memory access controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Combined read/write cycle for a direct memory access controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Combined read/write cycle for a direct memory access controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1471389