Dynamic magnetic information storage or retrieval – General processing of a digital signal – Head amplifier circuit
Reexamination Certificate
1998-12-16
2001-11-06
Neal, Regina Y. (Department: 2751)
Dynamic magnetic information storage or retrieval
General processing of a digital signal
Head amplifier circuit
C360S051000
Reexamination Certificate
active
06313962
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to magnetic storage systems, and more particularly to combined read and write VCO for data channels.
2. Description of Related Art
In computer systems, information is stored on magnetic storage systems such as hard drives. Data is stored in a series of spiral or concentric rings known as tracks. The data includes streams of magnetic polarity transitions on the disk surface. A number of schemes are used to detect these transitions and data.
One data detection method is a peak detection system. Peak detection ensures the accurate reading of the magnetic transitions that encode the bits on a disk. These magnetic transitions are given a 1 or 0 value. In reading two adjacent transitions, i.e. two adjacent
1
s, the signals can interfere with each other and cancel each other out. To avoid this “inter-symbol” interference the data must be encoded which results in a coded data string that is about 50% longer than an uncoded string. This extended code takes up disk space and limits bit density.
PRML overcomes this by comparing a data string with all known possible data strings to determine its identity. A PRML channel can be used to achieve high data density in writing and reading digital data on magnetic recording disks. This technique takes inter-symbol interference into account rather than tying to eliminate it. The result is a far more efficient coding scheme that permits more bits to be encoded on a track.
The actual control mechanism for PRML is in the selection of the partial response targets or polynomials which are chosen. In a PRML channel, the incoming signal from the preamplifier is first equalized and then sampled according to the partial response regimen selected. These samples are then fed to the maximum likelihood sequence detection circuitry, commonly a Viterbi detector, which identifies a sequence of bits read from the drive that would be the most likely to cause this sampled pattern. Since detection is applied to a sequence of bits rather than a series of individual bits, the PRML detector does a much better job of resolving marginal bit transitions, and therefore tolerates a much higher bit density (hence lower SNR) without increasing bit error rates.
PRML channels require timebase generation during write operations and timebase capture during read operations. Previous channel designs used separate voltage controlled oscillators (VCOs) for read and write operations. The write VCO (timebase generator) runs the entire time the channel is enabled due to its slow response. The write VCO can not be stopped during a read because, after the read ends and the write VCO is restarted, the write VCO takes too long to reacquire an accurate timebase, thus forcing the DASD product to wait until the channel was ready before performing a write operation and having an adverse effect on performance.
The read VCO (timebase capture) also runs the entire time the channel is enabled due to the need for quick timing capture at the beginning of every read. When the channel is not reading, the read VCO is locked to the write VCO, so the read VCO is at the correct frequency when a read begins. This substantially improves the time required to capture the frequency and phase of the signal being read, since the frequencies should nearly match, even though spindle speed tolerance can induce a difference.
Thus, previous channels have all used separate read and write VCOs for performance reasons, but all suffer from the same problems. For example, excess power is used during read operations due to the write VCO. Also, providing two VCOs and associated circuitry increases the chip size. Further, increased clock noise coupling occurs during read operations due to the write VCO
It can be seen that there is a need for a combined read and write VCO for data channels.
SUMMARY OF THE INVENTION
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a combined read and write VCO for data channels.
The present invention solves the above-described problems by providing a combined read and write VCO for data channels that shares a common loop capacitor while providing optimal read and write VCO loop responses, and allows the VCO to relock to the write timebase after a read very quickly while maintaining an accurate timebase.
A system in accordance with the principles of the present invention includes an oscillator providing an output signal having a frequency that varies proportionately to an oscillator input signal and an adjustable voltage source, the adjustable voltage source having a first configuration for a write mode and a second configuration for a read mode, and the adjustable voltage source providing the oscillator input signal to the oscillator in response to receiving an input current signal.
Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that the adjustable voltage source includes a first and second capacitor coupled in series and a switch coupled across the second capacitor, the switch being open to provide the first configuration and closed to provide the second configuration.
Another aspect of the present invention is that the oscillator further includes a transconductance amplifier for receiving the input signal from the adjustable voltage source and converting the input signal to a current signal having a first current value, a current modifier, the current modifier providing a current change signal according to whether a write or a read mode is selected and whether an acquisition or track mode is selected, an adder, coupled to the transconductance amplifier and the current modifier, the adder modifying the current signal according to the current change signal to produce an adjusted current signal and a current controlled oscillator, coupled to the adder, the current controlled oscillator receiving the adjusted current signal and producing an output signal having a frequency proportional to a magnitude of the current of the adjusted current signal.
Another aspect of the present invention is that the current phase signal provides up to a ten percent phase change when the acquisition mode is selected.
Another aspect of the present invention is that the current phase signal provides up to a one percent phase change when the read mode and the tracking mode are selected.
Another aspect of the present invention is that the current phase signal provides a 0.5 percent phase change when the write mode and the tracking mode are selected.
Another aspect of the present invention is that the input current signal has a range of ±1.0 milliamp when the acquisition mode is selected.
Another aspect of the present invention is that the input current signal has a range of ±62.5 microamps when the read mode and the tracking mode are selected.
Another aspect of the present invention is that the input current signal has a range of ±32.0 microamps when the write mode and the tracking mode are selected.
Another aspect of the present invention is that the adjustable voltage source includes a write capacitor and a read capacitor coupled in series and a switch coupled across the read capacitor, the switch being open to provide the first configuration, the first configuration being a read mode, and closed to bypass the read capacitor and provide the second configuration, the second configuration being a write mode.
Another aspect of the present invention is that a predetermined delay is used before closing the switch to provide a predetermined delay between transitioning from the read mode to the write mode to maintain a correct frequency for back-to-back read operations.
Another aspect of the present invention is that the delay includes a one microsecond delay.
These and various other advantages and features of novelty which
Galbraith Richard L.
Poss Joe Martin
Stanek David James
Windler Peter John
Hollingsworth Mark A.
International Business Machines - Corporation
Merchant & Gould
Neal Regina Y.
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