Combined plasma/liquid cleaning of substrates

Details Combined plasma/liquid cleaning of substrates Combined plasma/liquid cleaning of substrates

2001-03-08

2003-04-15

Markoff, Alexander (Department: 1746)

Cleaning and liquid contact with solids

Processes

Including application of electrical radiant or wave energy...

C134S001300, C134S026000, C134S030000, C134S037000, C134S095200, C134S095300, C134S902000, C156S345350, C156S345550

Reexamination Certificate

active

06546938

ABSTRACT:

BACKGROUND OF THE INVENTION
Modern integrated circuits and computer chips have two levels of fabrication: the “front-end-of-line”, (FEOL), which consists of structured portions of silicon and silicon-containing compounds, which are built into the silicon wafers using lithography, thin film deposition, and ion implantation techniques; and the “back-end-of line”, (BEOL), components, which wire or connect different regions of a device or different devices, and which are built on top of the wafer surface. Back-end-of-line fabrication typically involves a number of metallization and dielectric isolation films or steps.
In order to make a device operate faster, circuits are commonly “shrunk” in the FEOL fabrication process, as this reduces the electron travel distance, and better conductors are used in the BEOL. This is especially important since smaller lines carrying current also have greater resistance. Traditionally, the BEOL fabrication process has employed aluminum metallurgy in interconnection technology for the reason that aluminum can be easily deposited and etched to make the required wires and contacts needed to connect different devices and different portions of the same device. However, the use of copper in place of aluminum provides an important advantage because copper has a lower resistivity than does aluminum. This lower resistivity of copper allows faster interconnection response due to the resultant lower resistance/capacitance (RC) time constant. Copper is also more resistant to corrosion than aluminum circuitry.
Unfortunately, copper interconnects on a silicon or other semiconductor device presents certain technological problems. As opposed to aluminum, copper cannot be plasma etched because the halide salts of copper are involatile at the relatively low temperatures required for silicon processing. In contrast, aluminum etching is often accomplished by exposing the Al film on a substrate to chlorine-containing plasma, which generates atomic chlorine. The chemical reaction of the plasma-generated atomic chlorine with the Al on the substrate produces the reaction product, AlCl
3
. This aluminum salt has sufficiently high vapor pressure that it is pumped away by the vacuum system that is always used in low pressure plasma etching. The chlorine-containing feedgas is typically a mix of BCl
3
and/or Cl
2
. To aid in the volatilization and removal of the Al salt, the wafer is heated to 200-300 deg. C., which increases the vapor pressure of the Al salt, resulting in its evaporation from the wafer. These temperatures are acceptable to a wafer and do not cause harm to the materials present on the wafer, nor the structure of the device.
Unlike Al, when exposed to a chlorine or fluorine-containing reactive plasma, copper forms a reaction product, which has a low vapor pressure and thus cannot be pumped away by the vacuum system. This inhibits, and essentially stops, the reaction process because the buildup of the copper fluoride (CuF
2
) or copper chloride (CuCl
2
) films form a passivating surface film on the wafer, which prevents reactive chlorine or fluorine atoms from reaching the unreacted copper surface. It would be possible to etch copper in plasmas, by subjecting the wafer to very high temperatures, in the range of 400-700 C. At these temperatures, the copper chloride has sufficient vapor pressure to be pumped away. However, these high temperatures irreversibly damage the devices on the wafer. Because of this, other techniques are required to etch copper. While these techniques are meticulous, and typically involve the use of multiple lift-off steps, in which a layer below the copper film is attacked and then peeled off, no suitable alternative exists at this time. This is because the etching process for the interconnect levels on the wafer needs to achieve high directionality (anisotropy) to produce fine lines.
The present invention relates to another step in copper interconnect technology in which directionality is not required. As part of the developed art in copper process technologies for silicon wafers, it has been shown that it is important to remove unwanted copper film deposits from the beveled edge of a wafer, as well as from the back side edge, and the front edge of the wafer. The copper deposited in these regions is the result of film deposition method used for putting copper films on silicon wafers. Whereas copper is desirable as an interconnect material, the presence of copper on these other portions of the silicon wafer (i.e., the beveled edge of the wafer, the backside of the wafer, and the outermost circumference of the wafer in the so-called “edge exclusion” zone) is considered undesirable because copper in these regions can contaminate the equipment used for processing wafers. Accordingly, it is desirable to remove any copper present in the “edge-exclusion” zone, which typically is 2-4 mm from the periphery of the wafer, and from the other cited regions of the wafer. If not removed from the wafer, copper present in these regions could contaminate the robotic handling system for the tools with which the wafers are processed.
Copper contamination within a process tool could be a cause of yield loss because stray copper can change the electrical properties of the bulk silicon and alter the operation of a device. On the front surface of the wafer, protection of the silicon is achieved by using a barrier layer, usually titanium. However, this protection is missing from the edges of the wafer and from the backside of the wafer. In sum, it is vitally important to remove the copper film from the front edge exclusion zone, the wafer bevel, and the rear edges of the wafer so that serious contamination problems are prevented. Current means of achieving this require exposure of the wafer to acid sprays, because such acids are capable of dissolving copper. This approach works, but is labor intensive, requires additional process steps, and also generates hazardous chemical waste.
The present invention provides a cost-effective alternative to the use of these chemical solvents, which are presently used to remove contaminant copper from the beveled edge, front-side edge exclusion zone and the backside of silicon wafers. It allows edge cleaning of substrates and cleaning of selected portions of the substrate using a plasma and does not require exposure of the substrate to hazardous solvents or acids. It is a unique merging of both dry plasma technology with a gentle liquid rinsing process, something that would be impossible to achieve using conventional, low pressure plasmas, because this plasma process operates at pressures at, or close to atmospheric pressure. It partly accomplishes this through use of the technology described in U.S. Pat. No. 5,961,772, issued Oct. 15, 1999, to Selwyn The teachings of this patent are included herein for all purposes.
It therefore an object of the present invention to provide for isotropic cleaning of copper films from substrates.
It is another object of the present invention to provide for cleaning of copper films from specific regions of a substrate.
It is yet another object of the present invention to provide apparatus that allows copper to be used in integrated circuit fabrication.
It is yet another object of the present invention to provide an approach by which atmospheric pressure plasma processing is alternated with a liquid rinsing step to achieve material process capability that would either not be possible separately, or which would be onerous to achieve using a sequential low-pressure plasma, followed by a rinsing step.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
SUMMARY OF THE INVENTION
To achieve the foregoing and other o

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