Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By phase
Reexamination Certificate
1999-10-07
2001-08-14
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By phase
C327S005000, C327S012000
Reexamination Certificate
active
06275072
ABSTRACT:
BACKGROUND OF THE INVENTION
Timing circuits are used in digital circuits to generate and align clock signals. For example they are used to synthesize clocks at various frequencies in microprocessors and other computer circuits. They are also used to generate and recover bit clocks in data communication circuits. Most of these timing circuits take the form of a phase-locked loop (PLL) or a delay-locked loop (DLL). The design and analysis of these timing circuits is discussed in detail in Dally and Poulton,
Digital Systems Engineering,
Cambridge, 1998, pp. 428-447.
An example DLL is shown in FIG.
2
. Input aclk is delayed by five inverters
121
-
125
generating five equally-spaced clock phases, bclk-fclk. The phase comparator
126
compares phases bclk and fclk and outputs control signals up and down to charge pump
127
. The charge pump
127
transfers charge to or from capacitor
128
in response to the control signals to adjust the voltage on inverter supply line
129
. By adjusting the inverter supply voltage, the phase comparator and charge pump act to bring bclk and fclk into phase. Once the DLL control loop has converged, bclk and fclk are in phase, and clocks bclk to eclk have equally spaced phases 90-degrees apart (and complemented for the odd phases).
As illustrated in
FIG. 3
, if fclk is slow, i.e., its phase lags that of bclk, the phase comparator
126
asserts control signal up from the rising edge of bclk to the rising edge of fclk. The up signal causes the charge pump
127
to transfer charge to capacitor
128
, effectively pumping its voltage up. This voltage is buffered by voltage follower
130
to provide inverter supply voltage
129
. The increase in the inverter supply voltage reduces the delay of inverters
121
-
125
which reduces the phase difference between bclk and fclk. After many cycles of small adjustments, the phases of bclk and fclk are aligned.
The situation when felk is too fast is illustrated in FIG.
4
. Here the phase comparator
126
asserts control signal down from the rising edge of fclk to the rising edge of bclk. In response to this signal, charge pump
127
transfers charge from capacitor
128
reducing the capacitor voltage. This increases the delay of the inverters
121
-
125
which slows fclk to bring it into phase with bclk.
In the past, phase comparators have been constructed using flip-flops (c.f., Dally and Poulton pp. 431-433 and p. 617), exclusive-OR gates (c.f., Dally and Poulton pp. 433-434 and pp. 615-617), and sequential logic circuits (c.f., Dally and Poulton pp. 434-436, pp. 459-460, and pp. 617-620). The waveforms in
FIGS. 3 and 4
correspond to the output of a sequential phase-only comparator.
The logic diagram of a sequential phase-only comparator (described in Dally and Poulton pp. 459-460, and pp. 617-620) is shown in FIG.
5
. This circuit compares the phase of bclk and fclk and generates a pulse on up with width proportional to the phase difference if bclk leads fclk. If fclk leads bclk a pulse is generated on down with width proportional to the phase difference.
When fclk and bclk are exactly aligned, this circuit generates small, equal pulses on both up and down. Generating pulses on both outputs when fclk and bclk are aligned is necessary to prevent a dead band in the phase comparator response at the point of zero phase difference. If no pulses were generated when fclk and bclk are aligned, there would be a range of phase difference about zero, a dead band, where the phase comparator would produce no output and hence would not be able to control the phase difference in the proper direction.
The circuit of
FIG. 5
is an asynchronous sequential logic circuit that detects the rising edges of the clock signals. Gates
131
through
136
form a positive edge-triggered flip-flop that is set on the rising edge of bclk. Similarly gates
137
through
142
form a positive edge-triggered flip-flop that is set on the rising edge of fclk. After both rising edges have occurred, the output of gate
143
goes high resetting both flip flops. Thus, each output is high from the time its corresponding input rises until both outputs have gone high. The delays of the gates are adjusted to ensure that both outputs go high before gate
143
resets them, ensuring that there is no dead band in the phase response of the circuit.
A typical prior art charge pump is illustrated in FIG.
7
. This circuit accepts up and down inputs from the phase comparator and sources or sinks charge to output capacitor
111
. When input up is asserted it switches on FET
161
which enables current-source FET
104
to sink current from node
112
. This current is mirrored by current-mirror FETs
105
and
110
to source current onto the output. The duration of the current pulse on the output, and hence the charge deposited on capacitor
111
is directly proportional to the width of the up pulse. When the down input is asserted it switches on FET
162
which enables current source FET
109
to directly sink current from output capacitor
111
. The amount of charge removed from the capacitor is directly proportional to the width of the down pulse.
SUMMARY OF THE INVENTION
In accordance with the present invention, a phase comparator compares the phase of first and second timing signals. A window signal that is true during edges of the timing signals is applied with the timing signals to combinational circuitry, circuitry having an output which depends only on the state of the input. The combinational circuitry provides a phase comparison of the edges of the first and second timing signals as an output signal. A feedback circuit from the output signal may control the phase of at least one of the first and second timing signals to thus bring the two signals into proper phase.
Where a phase comparison of the rising edges of the first and second timing signals is made, the window signal is true during the rising edges of the timing signals and false during the falling edges of the timing signals. The window signal may be a phase shined version of one of the timing signals and may be derived from a counter.
The timing signals and their complements may be ANDed with the window signal. In a specific implementation, the output signal comprises an up signal and a down signal. The up signal is derived by ANDing the window signal with the first timing signal and the complement of the second timing signal, and the down signal is derived by ANDing the window signal with the second timing signal and the complement of the first timing signal.
In a preferred implementation, the output signal is generated by sourcing current to the output when the first timing signal leads a second timing signal and draining current from the output when the first timing signal lags the second timing signal. The current is sourced and drained to and from charge storage such as a capacitor. A feedback signal from the stored charge controls the phase of at least one of the first and second timing signals.
A phase comparison may be made on both the rising edges and the falling edges of the first and second timing signals. A comparison of falling edges of the first and second timing signals may be provided in second combinational circuitry. The second combinational circuitry receives a window signal which is true during the falling edges of the timing signals and false during the rising edges of the timing signals.
In a preferred implementation, the combinational circuitry which performs the comparison comprises a switching device gated by the window signal in series with a subcircuit of switching devices. The subcircuit includes a switching device gated by the first timing signal in series with a switching device gated by the complement of the second timing signal. The combinational circuitry may include two branches, a first branch gating current that causes current to source to the output storage and a second branch gating current that causes current to be sunk from the output storage. The first branch may be a pull down branch, and the combinational circuitry may include a current mirror t
Dally William J.
Farjad-Rad Ramin
Poulton John W.
Stone Teva J.
Yu Xiaoying
Cox Cassandra
Hamilton Brook Smith & Reynolds P.C.
Tran Toan
Velio Communications, Inc.
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