Combined MOS/memory transistor structure

Details Combined MOS/memory transistor structure Combined MOS/memory transistor structure

1983-12-15

1986-01-14

Larkins, William D.

357 59, 357 71, 357 233, H01L 2978, H01L 2704, G11C 1140

Patent

active

045648549

ABSTRACT:
A semiconductor device embodying this invention comprises a first conductive layer deposited on a semiconductor substrate to form a first element; a second conductive layer constituting a second element; and a third conductive layer superposed on the second conductive layer with an insulation layer interposed between said second and third conductive layers to form a third element. Only the second conductive layer formed from portions of the same layer of a conductive material is oxidized to provide an insulation layer; and consequently the first conductive layer is made thicker than the second conductive layer.

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