Combined integrated injection logic and transistor-transistor lo

Details Combined integrated injection logic and transistor-transistor lo Combined integrated injection logic and transistor-transistor lo

1980-07-11

1983-08-02

Chan, Eddie P.

Boots, shoes, and leggings

307475, 307459, G06F 300, G06F 748

Patent

active

043969801

ABSTRACT:
A microprocessor integrated circuit design has improved partitioning between integrated injection logic (I.sup.2 L) and transistor-transistor logic (T.sup.2 L) in the integrated circuit. An information bus structure incorporating a bidirectional input and output buffer and a bidirectional input and output multiplexer minimizes the number of internal bus lines in the integrated circuit. An improved T.sup.2 - I.sup.2 L interface circuit and structure supplies a T.sup.2 L input to a plurality of I.sup.2 L input stages, each having a restricted cross-sectional area resistor element in the base of an I.sup.2 L input transistor. A storage register in the integrated circuit has a multiplexer portion provided at each flip-flop circuit of the register. A high speed feed forward flip-flop circuit is employed in registers of the integrated circuit where speed is critical. An improved voltage regulator and current source combination in a programmable logic array (PLA) reduces PLA temperature sensitivity. A pair of I.sup.2 L clocking pulse input transistors in a T.sup.2 L master-slave circuit avoids capacitive coupling problems and allows the master-slave circuit to operate over a much wider temperature range. A cycle counter for the micro-processor integrated circuit implemented as an improved ripple down counter requires a minimum number of gates while avoiding significant delay in operation.

REFERENCES:
patent: 3757306 (1973-09-01), Boore
patent: 4085450 (1978-04-01), Tulpule
patent: 4106090 (1978-08-01), Erickson et al.
patent: 4155118 (1979-05-01), Lamiaux
patent: 4181934 (1980-01-01), Marenin

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