Combined FPLL and PSK data detector

Details Combined FPLL and PSK data detector Combined FPLL and PSK data detector

1987-03-12

1988-07-05

LaRoche, Eugene R.

Demodulators

Amplitude modulation demodulator

Having specific distortion, noise or other interference...

358 24, 3581951, 455208, 331 12, H04N 950

Patent

active

047557621

ABSTRACT:
An FPLL circuit has a first low pass filter and a limiter having a delay that is less than one half the duration of a data bit for developing binary PSK data and a pair of multipliers, a first of which is operated in phase with and the other of which is operated in phase quadrature with an incoming RF signal. The second multiplier is connected to a third multiplier, which is also supplied with the limiter output for stabilizing the loop in the presence of data. The output of the third multiplier is supplied to a low pass filter that has a delay that is greater than the duration of a data bit and this output supplies an oscillator that develops the 90.degree. phase displaced signals for the first two multipliers.

REFERENCES:
patent: 4072909 (1978-02-01), Citta
patent: 4091410 (1978-05-01), Citta

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