Combined floating-point logic core and frame buffer

Details Combined floating-point logic core and frame buffer Combined floating-point logic core and frame buffer

2002-10-04

2004-07-06

Chauhan, Ulka J. (Department: 2676)

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

C345S543000, C345S545000, C345S552000

Reexamination Certificate

active

06760033

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a graphics subsystem. More specifically, the invention relates to frame buffer and texture memory in a graphic subsystem.
(2) Background
Typical prior art systems use a texture memory and a frame buffer, both instantiated as separate commodity DRAM chips driven by a graphics controller. This use of commodity DRAMs has been widely accepted because it permits easy modification or expansion of the graphic subsystem, permitting either texture memory or frame buffer size to be easily enlarged. Unfortunately, separation of the frame buffer and texture memory has caused some consumer confusion since expansion of the frame buffer memory size does not expand the texture memory and vice versa. Furthermore, this separation requires separate control logic which increases cost. Additionally, insufficient bandwidth is also a chronic problem for graphical subsystems. Accordingly, the additional bandwidth necessary to retrieve texture data makes combining texture memory with frame buffer memory impractical in such systems.
Pixel quality both in number of colors and resolution is affected by the depth (or number of bits) used to represent the pixel. Common pixel representations use 24 bits, eight bits for each component, in red green blue (RGB) format. Higher end systems use many more bits per pixel. Such systems may employ from 128 bits per pixel all the way up to 1024 bits per pixel (including stencil buffer, overlay buffer, z-buffer and up to eight samples per pixel, depending on the format and whether double buffering is used). These deeper pixels require significant bandwidth to retrieve data from the frame buffer memory. To resolve this problem, designers have taken advantage of massive parallelization, often using forty or more (in at least one case, one hundred sixty) distinct DRAM chips interfacing with the graphics controller to achieve the bandwidth required to move these pixel sizes fast enough for quality graphical renderings. This large number of chips on a single board necessarily implies a vast number of pin interconnections. These interconnections increase manufacturing difficulty and correspondingly the possibility of graphical subsystem failure.
Another problem faced in prior art systems is aliasing, which causes edges to appear jagged. One solution to the full scene aliasing is multisample anti-aliasing. Unfortunately, multisample anti-aliasing exacerbates the bandwidth constraints discussed above. Moreover, it requires even larger amounts of memory to instantiate the frame buffer. For example, typical multisample anti-aliasing renders the image four to eight times larger than the image will be displayed. That larger rendered image is then filtered down to the appropriate size. However, this larger rendering requires moving four or eight times the amount of data and therefore requires four to eight times the amount of bandwidth.
In view of the foregoing, it would be desirable to be able to combine frame buffer and texture memory in a single unit while expanding bandwidth and simplifying manufacturing.
BRIEF SUMMARY OF THE INVENTION
A method and apparatus for graphical processing is disclosed. A logic core to perform pixel fragment manipulation and processing is instantiated on a single semiconductor substrate with one or more memory units. The memory units are dynamically segmentable into frame buffer and texture memory. Because the logic core is on the same substrate as the memory units, the bandwidth between the core and the memory is greatly increased.


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