Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-12-19
2004-01-27
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S561000, C330S259000
Reexamination Certificate
active
06683484
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits. More particularly, the present invention relates to integrated circuit input buffers.
BACKGROUND OF THE INVENTION
The input pins of an integrated circuit are coupled to input buffers for receiving input signals from off-chip. Depending on the application in which the integrated circuit is used, the input signal can be single-ended or differential. A single-ended signal represents data by the voltage level on the signal wire. This voltage level typically ranges from one voltage supply rail to the other. A differential input signal represents data by the relative voltages on two differential signal wires. Differential voltages are typically reduced significantly from the rail-to-rail voltage levels used by single-ended signals.
Is often desirable to provide an integrated circuit with the flexibility of operating with single-ended input signals or differential input signals. However, because the differential signaling levels are lower than the rail-to-rail signaling levels used by single-ended systems, most input buffers are designed to operate exclusively in either a single-ended mode or a differential mode. This limitation therefore requires an integrated circuit to be configured differently for receiving differential input signals than for receiving single-ended input signals.
For example, integrated phase-locked-loop (PLL) circuits use an external reference clock for high performance applications. The jitter performance of an integrated PLL is significantly impacted by jitter in the reference clock. A major component of reference clock jitter is noise that couples onto the wire bringing the reference clock from the input pin to the PLL phase detector. One method of minimizing the effects of noise coupling onto the reference clock line is to use a differential reference clock. While this method is often the best technical solution, it requires the use of differential oscillators, which are significantly more costly than standard single-ended oscillators. Thus, having an input buffer that can accept either a differential or a single-ended reference clock would provide the option of selecting either high performance or low cost.
There are two existing methods of providing the flexibility of accepting differential or single-ended input signals. The first is to design separate integrated circuits for differential and single-ended input signals, or to design a modular integrated circuit that can be customized by inserting a differential or single-ended input buffer depending on the application. The second method is to design the integrated circuit to accept only single-ended input signals and then implement an input level shifting network that generates an appropriate complementary signal from the single-ended input. However, these methods add additional complexity and cost.
Therefore, improved input buffers are desired, which are capable of accepting both differential and single-ended input signals.
SUMMARY OF THE INVENTION
One embodiment of the present invention comprises an integrated circuit input buffer, which includes a differential buffer, first and second average value circuits and a feedback amplifier and is selectively operable in a differential operating mode and a single-ended operating mode. The differential amplifier has first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The amplifier output is coupled to the second buffer input when the input buffer is in the single-ended operating mode and is decoupled from the second buffer input when the input buffer is in the differential operating mode.
Another embodiment of the present invention is directed to an integrated circuit input buffer, which includes a differential buffer, first and second average value circuits, a feedback amplifier and a switch. The differential buffer includes first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The switch selectively couples and decouples the amplifier output to and from the second buffer input and has a switch control input.
Another embodiment of the present invention is directed to an integrated circuit input buffer, which includes a signal input for receiving a single-ended input signal, a feedback output for providing a feedback signal, and a differential buffer having first and second buffer inputs and first and second buffer outputs. The first and second buffer inputs are coupled to the first signal input and the feedback output, respectively. A feedback circuit measures a difference between the average values of the first and second buffer outputs and sets a voltage of the feedback signal such that the difference is reduced.
REFERENCES:
patent: 5444579 (1995-08-01), Klein et al.
patent: 5798664 (1998-08-01), Nagahori et al.
patent: 6411145 (2002-06-01), Kueng et al.
patent: 2001087902 (2001-09-01), None
Kraus Justin J.
Kueng Jeffrey S.
Le Dinh T.
LSI Logic Corporation
Westman Champlin & Kelly
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