Combined decoder/adder circuit which provides improved access sp

Details Combined decoder/adder circuit which provides improved access sp Combined decoder/adder circuit which provides improved access sp

1995-01-25

1996-07-02

Envall, Jr., Roy N.

Boots, shoes, and leggings

364786, 36523006, 395375, G06F 700, G06F 750, G11C 800

Patent

active

055329470

ABSTRACT:
The present invention is directed toward an combined decoder/adder circuit which provides faster access to a cache in a microprocessor than implementations which include an adder circuit which is followed by a decoder circuit. By decoding the upper order bits of a first operand and then rotating the upper order bits of the first operand by the upper order bits of a second operand, followed by an additional shift by one which is enabled by a carry generator the overall speed of the critical path is greatly increased. Accordingly, the time needed for generating an effective address (EA) and therefore accessing the cache is significantly decreased. The present invention has significant utility in microprocessors in which the word line decode is the critical path.

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IBM Technical Disclosure Bulletin, vol. 23, No. 5, Oct., 1980 pp. 1770-1779.
IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun., 1984 pp. 915-920.
IBM Technical Disclosure Bulletin, vol. 33, No. 3B, Aug., 1990 pp. 187-188.

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