Combined consective byte update buffer

Details Combined consective byte update buffer Combined consective byte update buffer

1996-07-24

1999-04-06

Amsbury, Wayne

395853, 395854, G06F 1300

Patent

active

058929789

ABSTRACT:
An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.

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