Combined CMOS and NPN output pull-up circuit

Details Combined CMOS and NPN output pull-up circuit Combined CMOS and NPN output pull-up circuit

1994-12-20

1996-12-24

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327112, 327170, 327376, 327433, H03K 512

Patent

active

055876773

ABSTRACT:
A pull-up circuit including an NPN bipolar transistor, a P-MOS transistor connected in parallel with the bipolar transistor, a first CMOS inverter for receiving an input signal and controlling the P-MOS transistor, and a second CMOS inverter for receiving the output of the first inverter and controlling the bipolar transistor. An output stage includes the pull-up circuit and also includes a pull-down circuit comprising an N-MOS transistor, a second NPN bipolar transistor connected in parallel with the N-MOS transistor, a control circuit for switching on the second NPN bipolar transistor, and a third inverter whose input is connected to the output terminal and whose output controls the N-MOS transistor and provides a signal to the control circuit for switching off the second NPN bipolar transistor.

REFERENCES:
patent: 4103188 (1978-07-01), Morton
patent: 5126588 (1992-06-01), Reichmeyer et al.
patent: 5140190 (1992-08-01), Yoo et al.
patent: 5173623 (1992-12-01), Chau et al.
patent: 5237213 (1993-08-01), Tanoi
patent: 5276364 (1994-01-01), Wellheuser

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