Combined clock recovery/frequency stabilization loop

Details Combined clock recovery/frequency stabilization loop Combined clock recovery/frequency stabilization loop

1995-10-20

1996-11-19

Chin, Stephen

Pulse or digital communications

Receivers

Angle modulation

375211, 455 75, 455 76, 455119, 332107, 332123, 332126, H03D 318

Patent

active

055770746

ABSTRACT:
The effects of long-term drift in a local reference oscillator are compensated by dividing the local reference oscillator frequency by one of three divider patterns (nominal ratio, add a cycle, delete a cycle) so that the symbol clock of the remote terminal is equal to the outroute symbol rate. The number of add a cycle and delete a cycle divider patterns are counted and stored. The average of the number of add a cycle and delete a cycle patterns is used to control the transmit frequency of the remote terminal to correspond to the outroute symbol rate. Thus, the clock recovery process generates a frequency calibration number used to track the frequency of the remote terminal local reference oscillator and to adjust the transmit frequency of the remote terminal accordingly.

REFERENCES:
patent: 3611435 (1971-10-01), Cooper
patent: 4606049 (1986-08-01), Daniel
patent: 5404378 (1995-04-01), Kimura

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