Combined circuit configuration for a CMOS logic inverter and gat

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307451, 307445, H03K 1920

Patent

active

051873885

ABSTRACT:
A combined logic circuit includes an inverter and a logic gate that share a common first logic signal. The inverter has an input for receiving the first logic signal and an output for providing an inverted first logic signal. The logic gate has a first input for receiving the first logic signal and two or more secondary inputs for receiving secondary logic signals. The logic gate also includes first and second power supply nodes. The first power supply node receives the inverted first logic signal, thus actively controlling the logic function of the gate as well as eliminating a separate inverting transistor, while the second power supply node normally receives a power supply voltage. The output of the logic gate provides a predetermined logic function of the first and secondary logic signals that is equivalent to the prior art circuit. The combined logic inversion and predetermined logic function are accomplished with one less transistor than prior art circuits.

REFERENCES:
patent: 4649296 (1987-03-01), Shoji
patent: 4758744 (1988-07-01), Plus
patent: 4999529 (1991-03-01), Morgan, Jr. et al.

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