Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
1998-09-24
2001-04-24
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000, C438S704000, C438S712000, C438S720000
Reexamination Certificate
active
06221775
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the planarization of integrated circuit surfaces and, more particularly, to a process combining chemical mechanical planarizing and reactive ion etching steps which reduces inadvertent generation of surface defects in underlying layers during planarization.
BACKGROUND OF THE INVENTION
Integrated circuits are formed on a semiconductor substrate, such as silicon, silicon-germainium or gallium arsenide, by patterning films of various materials on the substrate. These patterns of films may be made of conductors or insulators such that complex electrical circuits are formed. Also, the films and the patterns in the films may be of different materials, which is essential for transistor and diode fabrication. During the processing of one substrate, millions of individual devices, which could constitute hundreds of individual “chips,” may be formed.
In order for each of the chips to function properly, it is essential that the desired pattern of the circuit design be properly replicated onto the substrate film. If there is a failure in the processing such that the pattern is not properly applied to the substrate for any of the devices, then it is possible that the entire chip will not function and will need to be discarded.
As the size of the devices and the separation between the devices decrease, more devices can be placed on a chip. The complexity of manufacturing the chip increases with a decrease in size and separation, however, and the tolerances for errors in processing dramatically decrease. To manufacture the layers of film without errors or defects, it is essential that the semiconductor wafer be flat or “planar.” Failure of the wafer to achieve flatness at any layer of material can cause errors at subsequently deposited levels.
The unit process operation used to ensure that the wafer is planar is chemical mechanical planarization. The chemical mechanical planarization process involves holding the semiconductor wafer against a rotating polishing pad surface at a controlled pressure. A polishing slurry that has an abrasive particle (such as alumina, silica, ceria, or zirconia) and has chemical etchants is flowed onto the pad to aid in the removal of material. Because of the rotating nature of the process and manner in which the wafer is pressed against the polishing pad, the material on the wafer that is furthest from the substrate is polished at the fastest rate while the material that is recessed is not polished at all. Thus, areas of the wafer surface that are protruding off the substrate the most are polished back to the recessed areas resulting in a finished, “planarized,” flat surface.
One of the ways in which chemical mechanical planarization is used is in metallization, or formation of the network of conducting wires that create the circuit. In this step, the objective is to create a pattern of wires of tungsten, aluminum, or copper that are separated by dielectric all within the same level of the chip. The method that is used, which is often referred to as damascene metallization, starts by uniformly depositing a conformal film of the dielectric, which is generally silicon dioxide (SiO
2
), phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG). The dielectric film is then patterned such that both trenches and holes are etched into the dielectric. Next, a thin layer (usually 10 to 100 nanometers (nm) thick) of liner material, such as titanium (Ti) and titanium nitride (TiN) or tantalum (Ta) and tantalum nitride (TaN), is deposited by physical vapor deposition (PVD), otherwise known as sputter deposition, or chemical vapor deposition (CVD). Finally, approximately 600 to 1,000 nm of the conductor, which is generally tungsten (W), copper (Cu), or aluminum (Al), is deposited so that the remainder of the trenches and holes are filled.
To isolate the individual conductor-filled trenches and holes from each other electrically, it is necessary to remove the excess conductor that is not in the trenches or holes. Although it is possible in principle to remove this metal by a chemical etch or a plasma reactive ion etch process, these processes are unacceptable because they tend to remove the conductor at nearly the same rate at the top of the trenches as in the trenches. Because it planarizes as it removes material, however, chemical mechanical planarization is exceedingly efficient at removing the excess metal.
The typical scheme to isolate the conducting wires is to use a primary polishing slurry, to polish off both the excess conductor and liner material. The polishing slurry, pad, and operating parameters of the chemical mechanical planarization process are specifically optimized for a high chip yield, at high removal rate of both the conductor and liner. The metal polishing slurry usually consists of alumina particles, from 100 to 500 nm in diameter, in an acidic (1<pH<4) environment, with between 0.1 and 0.6M concentration of oxidizer such-as hydrogen peroxide, ferric nitrate, or potassium iodate. The role of each ingredient has a special function. The oxidizer is added to chemically attack the metal and to enhance the polishing rate. Alumina, which is considerably harder than other abrasives such as silica, ceria, or zirconia, is usually used for a high rate of polishing of the metal and slow rate of polishing of oxide. Finally, the pH is acidic to prevent polishing of the silicon oxide.
There are a number of problems that can occur during the chemical mechanical planarization process which can adversely affect the chip yield. One of the biggest problems is erosion of the dielectric, which is caused by the variation of the pattern densities of conductors across the wafer. In large regions where there is a high concentration of the metal, there is often not enough dielectric to define a polishing plane. As a result, the polishing pad tends to flex and polish the dielectric that is in the region, resulting in a large area of the wafer that is substantially lower than other places on the chip. This non-planarity tends to replicate to the next level of the chip, where it can be filled with metal or cause alignment issues.
Another problem is that the primary slurry described above can cause scratches in the dielectric, which will replicate to further levels. Although scratches are somewhat inevitable in a polishing process,. the severity of these scratches are increasing with the use of lower dielectric constant materials such as organic-based or aero-gel-based dielectrics. To eliminate the effects of severe scratches, the primary polish is usually followed by a second “touch-up” chemical mechanical planarization step that removes between 10 and 100 nm of the dielectric. This step is often accomplished with a silica-based, alkaline slurry that is formulated for a high oxide removal rate. The application of this second planarizing step is not without its own problems. This step often causes erosion of oxide in regions of high pattern density, which is the creation of more topography. In addition, because the touch-up slurry is alkaline, while the primary slurry is acidic, precipitates can form on the wafer when these two slurries contact, creating a problem in cleaning the surface.
Another problem that often occurs during chemical mechanical planarization is residual metal after polishing. Often the residual metal results from topography that exists on the wafer before the deposition of the liner materials. These regions of non-planarity might be caused by erosion or scratches at a previous level, which then replicate up through the deposition of the oxide and are then filled with the metal. Because these defects represent metal that is below the plane to which one is trying to polish, they are virtually impossible to remove via chemical mechanical planarization. That is, chemical mechanical planarization is very poor at removing material that is recessed into the dielectric. As a result, these metal-filled scratches and regions of erosion represent regions of unremoved, excess metal that tends to result
Ference Thomas G.
Landers William F.
MacDonald Michael J.
Mlynko Walter E.
Murray Mark P.
Anderson Matthew
International Business Machines Corp.
Ratner & Prestia
Utech Benjamin L.
Walter, Jr. Esq. Howard J.
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