Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-11-03
2004-02-17
Rose, Robert A. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S065000
Reexamination Certificate
active
06692339
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of electronic devices. More particularly, the invention provides a device for planarizing a film of material of an article such as a semiconductor wafer. In an exemplary embodiment, the present invention provides an improved substrate support for the manufacture of semiconductor integrated circuits. However, it will be recognized that the invention has a wider range of applicability; it can also be applied to flat panel displays, hard disks, raw wafers, MEMS wafers, and other objects that require a high degree of planarity.
The fabrication of integrated circuit devices often begins by producing semiconductor wafers cut from an ingot of single crystal silicon which is formed by pulling a seed from a silicon melt rotating in a crucible. The ingot is then sliced into individual wafers using a diamond cutting blade. Following the cutting operation, at least one surface (process surface) of the wafer is polished to a relatively flat, scratch-free surface. The polished surface area of the wafer is first subdivided into a plurality of die locations at which integrated circuits (IC) are subsequently formed. A series of wafer masking and processing steps are used to fabricate each IC. Thereafter, the individual dice are cut or scribed from the wafer and individually packaged and tested to complete the device manufacture process.
During IC manufacturing, the various masking and processing steps typically result in the formation of topographical irregularities on the wafer surface. For example, topographical surface irregularities are created after metallization, which includes a sequence of blanketing the wafer surface with a conductive metal layer and then etching away unwanted portions of the blanket metal layer to form a metallization interconnect pattern on each IC. This problem is exacerbated by the use of multilevel interconnects.
A common surface irregularity in a semiconductor wafer is known as a step. A step is the resulting height differential between the metal interconnect and the wafer surface where the metal has been removed. A typical VLSI chip on which a first metallization layer has been defined may contain several million steps, and the whole wafer may contain several hundred ICs.
Consequently, maintaining wafer surface planarity during fabrication is important. Photolithographic processes are typically pushed close to the limit of resolution in order to create maximum circuit density. Typical device geometries call for line widths on the order of 0.5 &mgr;m. Since these geometries are photolithographically produced, it is important that the wafer surface be highly planar in order to accurately focus the illumination radiation at a single plane of focus to achieve precise imaging over the entire surface of the wafer. A wafer surface that is not sufficiently planar, will result in structures that are poorly defined, with the circuits either being nonfunctional or, at best, exhibiting less than optimum performance. To alleviate these problems, the wafer is “planarized” at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel-interconnection schemes and circuit features are scaled to submicron dimensions, the required degree of planarization increases. As circuit dimensions are reduced, interconnect levels must be globally planarized to produce a reliable, high density device. Planarization can be implemented in either the conductor or the dielectric layers.
In order to achieve the degree of planarity required to produce high density integrated circuits, chemical-mechanical planarization processes (“CMP”) are being employed with increasing frequency. A conventional rotational CMP apparatus includes a wafer carrier for holding a semiconductor wafer. A soft, resilient pad is typically placed between the wafer carrier and the wafer, and the wafer is generally held against the resilient pad by a partial vacuum. The wafer carrier is designed to be continuously rotated by a drive motor. In addition, the wafer carrier typically is also designed for transverse movement. The rotational and transverse movement is intended to reduce variability in material removal rates over the surface of the wafer. The apparatus further includes a rotating platen on which is mounted a polishing pad. The platen is relatively large in comparison to the wafer, so that during the CMP process, the wafer may be moved across the surface of the polishing pad by the wafer carrier. A polishing slurry containing chemically-reactive solution, in which are suspended abrasive particles, is deposited through a supply tube onto the surface of the polishing pad.
CMP is advantageous because it can be performed in one step, in contrast to past planarization techniques which are complex, involving multiple steps. Moreover, CMP has been demonstrated to maintain high material removal rates of high surface features and low removal rates of low surface features, thus allowing for uniform planarization. CMP can also be used to remove different layers of material and various surface defects. CMP thus can improve the quality and reliability of the ICs formed on the wafer.
Chemical-mechanical planarization is a well developed planarization technique. The underlying chemistry and physics of the method is understood. However, it is commonly accepted that it still remains very difficult to obtain smooth results near the center of the wafer. The result is a planarized wafer whose center region may or may not be suitable for subsequent processing. Sometimes, therefore, it is not possible to fully utilize the entire surface of the wafer. This reduces yield and subsequently increases the per-chip manufacturing cost. Ultimately, the consumer suffers from higher prices.
It is therefore desirable to improve the useful surface of a semiconductor wafer to increase chip yield. What is needed is an improvement of the CMP technique to improve the degree of global planarity that can be achieved using CMP.
SUMMARY OF THE INVENTION
The present invention achieves these benefits in the context of known process technology and known techniques in the art. The present invention provides an improved planarization apparatus for chemical mechanical planarization (CMP). Specifically, the present invention provides an improved planarization apparatus that provides multi-action CMP, such as orbital and spin action, to achieve uniformity during planarization. The present invention further provides combined cleaning capability with CMP process capability to eliminate or reduce cleaning requirements in a separate module from the CMP process.
In accordance with an aspect of the present invention, a method for chemical-mechanical planarization of an object comprises performing a first planarization of the object using a first polishing pad having a smaller surface area than the object being planarized in a processing module; and cleaning the object in the processing module.
In some embodiments, cleaning the object comprises scrubbing the object. The object may be scrubbed using a PVA sponge. Cleaning the object may comprise applying ultrasonic energy to the object. The ultrasonic energy may be applied to the object using an ultrasonic wand, ultrasonic shower, or an ultrasonic nozzle. In specific embodiments, the object is precleaned in the processing module, and the object is cleaned in a separate cleaning module. Prior to cleaning the object in the processing module, a second planarization of the object may be performed using a second polishing pad having a smaller surface area than the object being planarized in the processing module. The second polishing pad may be different in fineness from the first polishing pad.
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patent: 5897426 (1
Rose Robert A.
Strasbaugh
Townsend and Townsend / and Crew LLP
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