Combined adder and decoder digital circuit

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G06F 750

Patent

active

057107319

ABSTRACT:
An address used to access on-chip memory is calculated by summing two binary numbers to obtain an N-bit address. The N-bit address is decoded into a one-out-of-2.sup.N signal to select the addressed memory location. Instead of performing these operations sequentially, the addition and decoding are done at the same time, saving time and power and enabling changes to microprocessor organization and operation that enhance performance.

REFERENCES:
patent: 5532947 (1996-07-01), Potter et al.

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