Combinational logic circuit, system and method for eliminating b

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Unwanted signal suppression

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Details

327552, 327 34, 327311, 327166, H03K 500

Patent

active

057480346

ABSTRACT:
A host adapter of a computer system includes combinational logic circuit eliminating both positive and negative-glitches from an input signal. The circuit comprises two NAND gates and two delay elements in one embodiment. The delay introduced by second delay element is twice that of the first delay element. The first delay element receives as input the input signal. The first NAND gate receives as inputs the input signal and the output of the first delay element. The second delay element receives as input the output of the first NAND gate. The second NAND gate receives as inputs the output of the first NAND gate and the output of the second delay element. The output of the second NAND gate comprises the input signal with both positive and negative glitches having a duration of less than the delay of the first delay element eliminated. In a second embodiment, the two NAND gates are replaced by two NOR gates.

REFERENCES:
patent: 5184032 (1993-02-01), Leach
patent: 5198710 (1993-03-01), Houston
patent: 5265038 (1993-11-01), Kwok
patent: 5440178 (1995-08-01), McClure

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