Combinational delay circuit for a digital frequency multiplier

Details Combinational delay circuit for a digital frequency multiplier Combinational delay circuit for a digital frequency multiplier

1998-05-29

2002-08-27

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S152000, C327S153000, C327S158000, C327S161000

Reexamination Certificate

active

06441657

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a combinational delay circuit for a digital frequency multiplier and, more particularly, to a combinational delay circuit capable of fine adjustment of a delay time.
(b) Description of the Related Art
A digital frequency multiplier is generally used for generating a clock signal having a higher frequency and a clock phase in synchrony with the phase of an input reference clock signal. Such a digital frequency multiplier is described, for example, by T. Shimizu in “A Multimedia 32b RISC Microprocessor with 16 Mb DRAM”, ISSCC Digest of Technical Papers, 1996 IEEE International Solid-state Circuit Conference, pp.216 to 217, Feb. 1996. Patent Publications U.S. Pat. Nos. 5,422,835 and 5,530,837 also describe related devices.
FIG. 1
shows a conventional combinational delay circuit in a frequency multiplier capable of quadruple-multiplying the clock frequency of a reference clock signal. Four delay sets each including an individual delay circuit
101
,
102
,
103
or
104
and a selector
105
,
106
,
107
or
108
are serially cascaded from one another for receiving a reference (first) clock signal
111
to generate second through fifth clock signals
112
to
115
. In each delay set, the delay time of the delay circuit
101
,
102
,
103
or
104
is controlled by a corresponding one of the selectors
105
,
106
,
107
and
108
to have a plurality of unit delay times (t
d
), wherein t
d
is a unit delay time effected by each of the delay segments having an equal configuration.
A phase comparator
109
compares the fifth clock signal
115
against the reference clock signal
111
to supply either UP-signal
116
or DOWN-signal
117
to an UP/DOWN (U/D) counter
110
depending on the phase of the fifth clock signal
115
relative to the phase of the reference clock signal
111
. The U/D counter
110
supplies a control signal
118
for controlling the selectors
105
to
108
to equalize the phase of the fifth clock signal
115
with that of the reference clock signal
111
.
By the above control, since time delays of the respective delay circuits
101
to
104
are controlled by the single control signal
118
, the timing difference between each consecutive two of the clock signals
112
to
115
is equal to ¼ of the clock cycle of the reference clock signal
111
. By making a logical sum (OR) of the four clock signals
112
to
115
, a quadruple-multiplication of the reference clock signal
111
can be effected to generate a clock signal having a quadruple-multiplied frequency.
Table 1 shows the relationship between the desired total phase delay of the cascaded delay circuits
101
to
104
and the delays actually effected by the respective delay circuits
101
to
104
in the combinational delay circuit of FIG.
1
.
TABLE 1
Total
Delay
Delay
Delay
Delay
phase
circuit
circuit
circuit
circuit
delay
101
102
103
104
1
1
1
1
1
2
1
1
1
1
3
1
1
1
1
4
1
1
1
1
5
2
2
2
2
6
2
2
2
2
7
2
2
2
2
8
2
2
2
2
9
3
3
3
3
10
3
3
3
3
11
3
3
3
3
12
3
3
3
3
13
4
4
4
4
14
4
4
4
4
15
4
4
4
4
16
4
4
4
4
17
5
5
5
5
18
5
5
5
5
19
5
5
5
5
20
5
5
5
5
Table 2 shows the relationship between the total phase delay and the outputs
112
to
115
of the respective delay circuits
101
to
104
, which is obtained from Table 1.
TABLE 2
Total
Output
Output
Output
Output
phase
clock
clock
clock
clock
delay
112
113
114
115
1
1
2
3
4
2
1
2
3
4
3
1
2
3
4
4
1
2
3
4
5
2
4
6
8
6
2
4
6
8
7
2
4
6
8
8
2
4
6
8
9
3
6
9
12
10
3
6
9
12
11
3
6
9
12
12
3
6
9
12
13
4
8
12
16
14
4
8
12
16
15
4
8
12
16
16
4
8
12
16
17
5
10
15
20
18
5
10
15
20
19
5
10
15
20
20
5
10
15
20
As shown in Tables 1 and 2, the frequency multiplier having the combinational delay circuit described above generates output clock signals having a unit delay which is a quadruple of the unit delay time (t
d
) of each delay circuit. More specifically, the resultant quadruple frequency multiplier cannot adjust the time delay as fine as within four times the unit delay time of each delay circuit, and the error of the clock cycle of the clock signal generated by the frequency multiplier is as high as 3×t
d
at a maximum.
Specifically, if a total phase delay of 5 unit delays (5×t
d
) is to be effected, for example, each delay circuit selects 2 delay units (2×t
d
), whereby the output of the fifth clock signal
115
has a phase delay of 8 unit delays (8×t
d
) with respect to the reference clock signal
111
, which means the presence of an error of 3×t
d
in the timing of the clock pulse generated by the fifth delay circuit and preceding the clock pulse corresponding to the next pulse in the reference clock signal.
More generally, the error of the phase of the clocks in the output of the frequency multiplier after the logical sum of the respective outputs of the delay circuits resides mostly at specified clocks.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a combinational delay circuit for use in a frequency multiplier, which is capable of outputting a multiplied clock signal having a minimum adjustable delay time substantially equal to the unit delay time of the delay segments of the delay circuits.
It is another object of the present invention to provide a combinational delay circuit, wherein errors of the phase of the clock pulses are substantially uniformly distributed among the clock pulses.
The present invention provides, in one aspect, a combinational delay circuit comprising a first delay circuit having at least one basic delay line including a plurality of cascaded delay segments each effecting a unit time delay, a latch array having a plurality of latch elements each receiving an output from a corresponding one of the delay segments, a plurality of second delay circuits coupled to one another in a cascaded configuration, each of the second delay circuits having a delay element corresponding to said delay line for effecting a time delay substantially equal to the unit time delay, the delay element in each of the second delay circuits receiving an output from a corresponding one of the latch elements by responding to an output from a preceding one of the second delay circuits in terms of the cascaded configuration.
The present invention also provides, in another aspect, a combinational delay circuit for multiplying a frequency of an reference clock signal, comprising a plurality of cascaded delay sets each including a delay circuit having a plurality of cascaded delay segments, each such delay segment effecting a unit time delay; a selector for selecting an output from one of the delay segments as an output of the delay sets, a phase comparator for comparing the phase of an output of a last stage of the cascaded delay circuits against the phase of the reference clock signal, to output a phase difference signal, and a control section for responding to the phase difference signal to control one of the selectors for the selection of one of the delay circuits, the one of the selectors being specified based on a predetermined order of selection depending on the phase difference signal.
In accordance with the combinational delay circuit of the present invention, a frequency multiplier having the combinational delay circuit allows a fine adjustment of the clock delay with respect to the reference clock. In addition, the timing of the clock pulses is controlled so that the error is substantially distributed among the clock pulses.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.


REFERENCES:
patent: 5216301 (1993-06-01), Gleeson, III et al.
patent: 5245231 (1993-09-01), Kocis et al.
patent: 5260608 (1993-11-01), Marbot
patent: 5321734 (1994-06-01), Ogata
patent: 5422835 (1995-06-01), Houle et al.
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 5530387 (1996-06-01), Kim
patent: 5544203 (1996-08-01), Casasanta et al.
patent: 5633608 (1997-05-01), Danger
patent: 5699003 (1997-12-01), Sae

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