Combination prefetch buffer and instruction cache

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395452, 395467, 395471, 36424342, 3649579, 36496422, 36496424, 364DIG1, 364DIG2, G06F 1300

Patent

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055862950

ABSTRACT:
A cache memory system features a combination instruction cache and prefetch buffer, which obviates any requirement for a bus interconnecting the cache and buffer and which also effectively allows the instruction buffer to write data into the cache with improved utilization of prefetched instructions and with decreased use of power and silicon space.

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