Combination nonvolatile memory using unified technology with...

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S185230

Reexamination Certificate

active

07339824

ABSTRACT:
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.

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Co-pending U.S. Appl. No. 09/891,782, filed Jun. 27, 2001, assigned to a common assignee, “A Novel 3 Stepwrite Operation Nonvolatile Semiconductor One-Transistor Flash EEPROM Memory”.
Supplementary Partial European Search Aplus Flash Technolgy, Inc. Report for EP 03 81 1234.

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