Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-12-12
2006-12-12
Phung, Anh (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185250
Reexamination Certificate
active
07149120
ABSTRACT:
A combination EEPROM and Flash memory is described containing cells in which the stacked gate transistor of the Flash cell is used in conjunction with a select transistor to form an EEPROM cell. The select transistor is made sufficiently small so as to allow the EEPROM cells to accommodate the bit line pitch of the Flash cell, which facilitates combining the two memories into memory banks containing both cells. The EEPROM cells are erased by byte while the Flash cells erased by block. The small select transistor has a small channel length and width, which is compensated by increasing gate voltages on the select transistor and pre-charge bitline during CHE program operation.
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Hsu Fu-Chang
Lee Peter W.
Ma Han-Rei
Tsao Hsing-Ya
Ackerman Stephen B.
Aplus Flash Technology Inc.
Saile Ackerman LLC
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