Combination nonvolatile integrated memory system using a...

Details Combination nonvolatile integrated memory system using a... Combination nonvolatile integrated memory system using a...

2007-02-13

2007-02-13

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185290

Reexamination Certificate

active

11025822

ABSTRACT:
A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile memory cells use a large positive programming voltage (+18V) applied to the word lines or select gating lines for programming the memory cells and a large negative erasing voltage (−18V) applied to the word lines or select gating lines for erasing the memory cells. The NOR-type Flash nonvolatile memory array is used to store code of embedded processor programs or application programs for smart cards. The EEPROM array is preferably used to store byte alterable data and NAND-type Flash nonvolatile memory array is used to store personalized biometric data such as Iris, DNA, facial picture and finger prints.

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Co-pending U.S. Appl. No. AP-02-007, filed Aug. 19, 2002, U.S. Appl. No. 10/223,208, assigned to the same assignee.
Co-pending U.S. Appl. No. AP-02-008, filed Jan. 24, 2003, U.S. Appl. No. 10/351,180, assigned to the same assignee.
Co-pending U.S. Appl. No. AP-02-009, filed Jan. 24, 2003, U.S. Appl. No. 10/351,179, assigned to the same assignee.

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