Column shift circuitry for high speed testing of semiconductor m

Details Column shift circuitry for high speed testing of semiconductor m Column shift circuitry for high speed testing of semiconductor m

1984-08-14

1987-06-02

Fleming, Michael R.

Excavating

365201, G06F 1100

Patent

active

046708782

ABSTRACT:
A semiconductor integrated circuit, such as a high-density, dynamic read/write memory containing an array of rows and columns of memory cells, is constructed to allow high speed testing to identify row line faults in one example, and to identify column or sense amplifier faults in another example. Row lines for the array in a dynamic RAM may contain detector circuits activated in a special test mode to produce a data output indicating integrity of each row line without requiring the access of the cells in the array in complex data patterns. The connection between bit lines in the array and sense amplifiers may be shifted or transposed in another embodiment to distinguish between column or sense amplifier faults; this construction also allows rapid loading of test patterns.

REFERENCES:
patent: 4414665 (1983-11-01), Kimura
patent: 4450560 (1984-05-01), Conner
patent: 4459685 (1984-07-01), Sud
patent: 4464747 (1984-08-01), Groudan et al.
patent: 4464750 (1984-08-01), Takematsu
patent: 4471472 (1984-09-01), Young

Affiliated with

Also associated with

Rating

Column shift circuitry for high speed testing of semiconductor m does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Column shift circuitry for high speed testing of semiconductor m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Column shift circuitry for high speed testing of semiconductor m will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-617965