Column selector circuit for shared column CMOS EPROM

Details Column selector circuit for shared column CMOS EPROM Column selector circuit for shared column CMOS EPROM

1992-03-06

1994-10-25

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365203, 365218, 36523006, 365900, G11C 1134

Patent

active

053595556

ABSTRACT:
A CMOS memory is disclosed which employs a column selector circuit that prevents write disturb in shared column EPROMs. When a selected memory transistor is programmed, disturb is prevented by selecting all columns on the source side of the selected memory transistor to be tied to the source programming voltage, and selecting all columns on the drain side of the selected memory transistor to be tied to the drain programming voltage. By reducing voltage differentials across non-selected memory transistors, write disturb is prevented. This may be implemented by employing shorting devices between all adjacent columns. When a memory transistor is selected, all the shorting devices except the one between the source and drain columns of the selected memory cell are enabled. This may be further improved to minimize the number of required select lines by employing a shorting device comprising transistors controlled by the normal select lines.

REFERENCES:
patent: 5027321 (1991-06-01), Park

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