Column select latch for SDRAM

Details Column select latch for SDRAM Column select latch for SDRAM

2001-03-20

2001-11-20

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S189050

Reexamination Certificate

active

06320816

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to synchronous memory devices and in particular the present invention relates to memory array access signals.
BACKGROUND OF THE INVENTION
Synchronous dynamic random access memory (SDRAM) devices operate by accessing memory cells in synchronization with a clock signal. The access speed of the device is therefore dependant upon the frequency of the clock. An increase in the clock frequency, therefore, will increase access speed. A problem is experienced when the clock frequency exceeds the process speed of internal memory cell access operations. For example, to access a column of a memory array, an address signal is decoded and column select circuitry is activated. A problem is experienced when the clock frequency exceeds the time needed to complete an access operation of a previous memory column. Thus, if an access is not completed prior to decoding a new column address, the currently accessed column may be prematurely closed.
To avoid some of the timing problems experienced in SDRAMs, the column address decode operation can be pipelined. Additionally, a column select latch can be used to latch a currently accessed memory column while the address of a new column is concurrently decoded, see 250 Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture, [Nagase] Takai et al., 1993 Symposium on VLSI Circuits-Digest of Tecnical Papers, pages 59-60 (May 19-21, 1993) incorporated herein by reference. The problem with this type of column decode and select circuitry is that a column is selected when a new select signal is latched. Thus, a new address must either be delayed from being latched until a current column access operation is completed, or slower clock frequencies must be used. Further, [Nagase] Takai et al. describes an SDRAM which uses a latch connected between a column decode circuit and the memory array. Thus, 256 latch circuits are required in a memory having eight address lines.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a SDRAM having a pipelined address decode which can efficiently delay a new column address until a current access operation is completed. Such a memory device will allow the use of higher clock frequencies.
SUMMARY OF THE INVENTION
The above mentioned problems with synchronous memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A synchronous memory is described which latches a decoded column select signal. The memory further provides an enable control for coupling the column select signal to a column of memory.
In particular, the present invention describes a synchronous memory device comprising a memory array of memory cells, the memory cells being arranged in addressable rows and columns, and address inputs for receiving a plurality of address signals. A column decode circuit is provided for decoding the plurality of address inputs and producing an output signal identifying a column of the memory array. A latch circuit is coupled to the column decode circuit for latching the output signal. A coupling circuit is electrically located between the latch circuit and a column select circuit. The coupling circuit electrically isolating the latch circuit from the column select circuit in response to an enable signal.
In an alternate embodiment, a synchronous memory device comprises a memory array of memory cells, the memory cells being arranged in addressable rows and columns, and address inputs for receiving a plurality of address signals. A first column decode circuit is provided for decoding some of the plurality of address inputs and producing a first output signal. A latch circuit is coupled to the first column decode circuit for latching the first output signal. A second column decode circuit for decoding some of the plurality of address inputs, and an enable circuit is coupled to the second column decode circuit and an enable signal, the enable circuit producing a second output signal. A coupling circuit is electrically located between the latch circuit and a column select circuit. The coupling circuit electrically isolating the latch circuit from the column select circuit in response to the second output signal.
In another embodiment, a method of selecting a column of memory cells in a synchronous memory device is described. The method comprises the steps of receiving a plurality of address signals on address input lines, and decoding the plurality of address signals to identify a column of memory cells. A column select signal is producedin response to the decoded plurality of address signals. The column select signal is latched, and coupled to a column select ccircuit in response to an enable signal.
In yet another embodiment, a method of selecting a column of memory cells in a synchronous memory device is described. The method comprises the steps of receiving a plurality of address signals on address input lines, and decoding some of the plurality of address signals to produce a first decoded signal. Additional ones of the plurality of address signals are decoded to produce a second decoded signal. The first decoded signal is latched, and a column select signal is produced in response to the first decoded signal, the second decoded signal, and an enable signal.


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