Column select latch for SDRAM

Details Column select latch for SDRAM Column select latch for SDRAM

1997-08-21

1998-11-10

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518905, 36523008, G11C 800

Patent

active

058354417

ABSTRACT:
A synchronous memory device is described which uses unique column select circuitry. The memory device pipelines address decode and column select operation to increase clock frequency. The column select circuitry includes latches and coupling circuits. The latches are used to latch a column select circuit. The coupling circuit isolates a column select signal from the memory cell columns until an enable signal is provided. The address decode can be combined with an enable signal to reduce the total number of latch circuits needed for a bank of memory cells.

REFERENCES:
patent: 4858190 (1989-08-01), Yamaguchi et al.
patent: 5124951 (1992-06-01), Slemmer et al.
patent: 5128897 (1992-07-01), McClure
patent: 5136546 (1992-08-01), Fukuda et al.
patent: 5526318 (1996-06-01), Slemmer et al.
patent: 5587961 (1996-12-01), Wright et al.
patent: 5598375 (1997-01-01), Yang et al.
patent: 5604714 (1997-02-01), Manning et al.
patent: 5615164 (1997-03-01), Kirihata et al.
patent: 5627791 (1997-05-01), Wright et al.
patent: 5636175 (1997-06-01), McLaury
patent: 5640351 (1997-06-01), Yabe et al.
patent: 5650976 (1997-07-01), McLaury
patent: 5706229 (1998-01-01), Yabe et al.
patent: 5729502 (1998-03-01), Furutani et al.
Fujiwara, et al., "A 200MHz 16Mbit Synchronous DRAM with Block Access Mode", 1994 Symposium on VLSI Circuits--Digest of Technical Papers, 79-80, (Jun. 9-11, 1994).
Nitta, Y., et al., "A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture", IEEE International Solid-State Circuits Conf., 376-377, (Feb. 1996).
Takai, et al., "250 Mbyte/sec Synchronous DRAM Using a 3-Stage-Pipelined Architecture", 1993 Symposium on VLSI Circuits--Digest of Technical Papers, 59-60, (May 19-21, 1993).
Yoo, J., et al., "A 32-Bank 1Gb DRAM with 1Gb/s Bandwidth", IEEE International Solid-State Circuits Conf., 378-379, (Feb. 1996).

Affiliated with

Also associated with

Rating

Column select latch for SDRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Column select latch for SDRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Column select latch for SDRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1524234