Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-01-18
2008-09-23
Dinh, Son (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
Reexamination Certificate
active
07428186
ABSTRACT:
A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates on the transition detection signals respectively outputted from the address transition detectors, and outputs a signal representing the results of the logical operation. A ready signal generator outputs a strobe ready signal having a predetermined enable period in response to an enabled state of the signal outputted from the detection signal coupler. A strobe signal generator generates a read strobe signal and a page address strobe signal for latch of the page address signals in response to the strobe ready signal. Page address buffers are enabled by the page address strobe signal, and latch the page address signals, thereby buffering the page address signals, a page address decoder which decodes the buffered page address signals respectively outputted from the page address buffers. And, a column selection signal generator outputs column selection signals respectively corresponding to the decoded page address signals in response to the read strobe signal.
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Dinh Son
King Douglas
Marshall & Gerstein & Borun LLP
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