Column multiplexer

Static information storage and retrieval – Addressing – Multiplexing

Patent

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Details

36518902, 257206, 326102, G11C 800

Patent

active

057779414

ABSTRACT:
A column select multiplexer for a memory array organized in modules, each module handling two sets or bunches each of a certain minimum number of bitline, is realized in a space opposite to the bitline terminations and the select transistors are realized along an uninterrupted active area strip by realizing isolation gates between adjacent diffusions of two distinct select transistors. The bitlines of the two bunches handled by a multiplexer module are preferably interleaved and the respective select transistors are realized along two parallel uninterrupted active area strips.

REFERENCES:
patent: 4570176 (1986-02-01), Kolwicz
patent: 4745084 (1988-05-01), Rowson et al.
patent: 5051917 (1991-09-01), Gould et al.
patent: 5369595 (1994-11-01), Gould et al.

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