Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-05-21
2003-01-21
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185290
Reexamination Certificate
active
06510084
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to electrically-erasable, programmable read-only memories (EEPROMs). In particular, the present invention relates to column decoders with improved resistance to gate oxide breakdown.
FIG. 1
is a circuit diagram of a conventional EEPROM
50
. Bit lines
52
(columns) run vertically, and word lines
54
(rows) run horizontally. Connecting the bit lines
52
and the word lines
54
are cell transistors
56
. The cell transistors
56
act as memories to store the data bits desired to be held by the EEPROM
50
. A common source
58
connects the cell transistors
56
. The ellipsis (three dots) in the figure represent additional rows and columns that are not illustrated. In an exemplary embodiment, the EEPROM
50
contains 16 bit lines.
Bit line discharge transistors
60
function to discharge a selected bit line. Each gate of the bit line discharge transistors
60
is coupled to a corresponding one of the column decoder circuits
70
(see FIG.
2
).
Bit line selection transistors
62
function to select one of the bit lines. Each gate of the bit line selection transistors
62
is coupled to a corresponding one of the column decoder circuits
70
(see FIG.
2
). In general, the bit line discharge transistor
60
a
and bit line selection transistor
62
a
associated with a given bit line
52
a
are coupled to one column decoder circuit, while those of another bit line are coupled to another column decoder circuit.
Selection transistors
64
function to further select a desired bit line. For example, two bit line selection transistors
62
may be controlled by the same column decoder circuit
70
. In such a case, the selection transistors
64
further select the one desired bit line. In an exemplary embodiment, each selection transistor
64
is associated with eight of the bit lines
52
.
FIG. 2
is a circuit diagram of a conventional column decoder circuit
70
. A NAND gate
72
couples inputs (A
0
, A
1
, A
2
)
74
through NOT gate
76
to NAND gate
78
, and a NOR gate
80
couples chip enable signal (CEB)
82
and erase signal (ERASE)
84
to the NAND gate
78
. The output of the NAND gate
78
is coupled to transistor
86
a,
and to
86
b
through a NOT gate
88
. The remaining transistors
90
are coupled to provide either a voltage of VPP or a ground connection to the column decoder output
92
, as determined by the signal output from the NAND gate
78
. The column decoder output
92
is coupled to the gates of transistors
60
and
62
(see
FIG. 1
) as appropriate.
In an exemplary embodiment, with 16 bit lines organized into two sets of eight bit lines, the column decoder circuits
70
associated with the transistors
60
and
62
have three inputs
74
(to select one of the eight bit lines in each set), and the column decoder circuits
70
associated with the transistors
64
have one input
74
(to select one of the two sets).
In a read operation, an appropriate one of the word lines
54
charges the gates of the associated cell transistors
56
to between about 2 and 5 volts. This selects the appropriate row. A desired one of the bit lines
52
is selected with the bit line selection transistors
62
(as controlled by the column decoder circuits
70
) and the selection transistors
64
. This selects the appropriate column. The common source
58
is at 0 volts and the selected bit line is between about 0.8 and 1 volts. An output of between about 3 and 4 volts is then detected by the sense amplifier (not shown).
In a write operation, the desired word line
54
is raised to a potential of between about 7 and 9 volts, the selected bit line
52
is between about 3 and 5 volts, and the common source
58
is at 0 volts. The transistors
60
,
62
and
64
coupled to the selected bit line
52
are at between about 7 and 9 volts.
Of course, an important feature of EEPROMs is their erasability. The problems involved in such an erasure operation are discussed below.
FIG. 3
is a cross-sectional view of a portion of EEPROM
50
(see FIG.
1
), generally formed on a P-substrate
94
. Each of the cell transistors
56
is formed with a deep N-well
96
and a P-well
98
. During an erasure operation, the gate of the cell transistor
56
is set to a potential level of −VPP (generally −10 volts) by the word line
54
, the source of the cell transistor
56
is set to float from the source line
58
, and the drain of the cell transistor
56
is set to float via the bit line
52
. Generally the float potential is between 9.3 and 9.5 volts due to a diode drop. The other regions of the cell transistor
56
are set to a potential level of +VPP (generally +10 volts less the junction built-in voltage of 0.7 volts) as shown in FIG.
3
. The gates of the bit line discharging transistor
60
and bit line selection transistor
62
are set to a potential level of 0 volts via output
92
of column decoder circuit
70
(see FIG.
2
).
In such a case, with the gates of the transistors
60
and
62
at zero volts, and the bit line
52
setting their drains to float at approximately 9.5 volts, there is a potential for gate oxide breakdown due to the voltage differential. To overcome this problem, conventionally, high-voltage transistors are used for the transistors
60
and
62
. These high-voltage transistors have a thick gate oxide and have a correspondingly large channel length. These high-voltage transistors
60
and
62
are represented in
FIG. 1
by the thickly-illustrated gates. However, because of the thick gate oxide, it becomes difficult to lay out these transistors in the allotted bit line pitch.
SUMMARY OF THE INVENTION
To overcome the above-noted problems, the present invention proposes two options. The first is to provide a bias voltage to the gates of the bit line selection and discharging transistors during the erasure operation. The second is to float the gates of the bit line selection and discharging transistors during the erasure operation.
REFERENCES:
patent: 5402382 (1995-03-01), Miyawaki et al.
patent: 5521866 (1996-05-01), Akaogi
patent: 5617359 (1997-04-01), Ninomiya
patent: 5719807 (1998-02-01), Sali et al.
patent: 5862079 (1999-01-01), Jinbo
Phan Trong
Townsend and Townsend / and Crew LLP
Winbond Electronics Corporation
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