Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2005-02-15
2005-02-15
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S145000
Reexamination Certificate
active
06856573
ABSTRACT:
A column decoder cell layout for use in a 1T/1C ferroelectric memory array includes a first column decoder section having two input nodes for receiving a first input/output signal and a first inverted input/output signal, two output nodes for providing a fist bit line signal and a first inverted bit line signal, and a column decode node for receiving a column decode signal, a second column decoder section having two input nodes for receiving a second input/output signal and a second inverted input/output signal, two output nodes for providing a second bit line signal and a second inverted bit line signal, and a column decode node for receiving the column decode signal, wherein the width of the column decoder cell is substantially the same as the width of two columns of 1T/1C memory cells used in the array.
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Allen Judith E.
Perkalis Joseph
Wilson Dennis R.
Burton Esq. Carol W.
Hogan & Hartson L.L.P.
Kubida, Esq. William J.
Le Vu A.
Ramtron International Corporation
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