Column decoder circuit for use with memory using multiplexed row

Details Column decoder circuit for use with memory using multiplexed row Column decoder circuit for use with memory using multiplexed row

1982-12-22

1986-01-28

Popek, Joseph A.

Static information storage and retrieval

Addressing

365203, G11C 1140

Patent

active

045675813

ABSTRACT:
A memory having multiplexed address inputs uses a column decoder which is deactivated during row address time and becomes activated during column address time. Access time and power dissipation are reduced since the column decoder need not be fully recovered after row address information has terminated and column address information is available.

REFERENCES:
patent: 4074237 (1978-02-01), Spampinato
patent: 4200917 (1980-04-01), Moench
patent: 4475181 (1984-10-01), Etoh et al.

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