Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-07-08
2004-06-08
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110, C365S185130, C365S230030, C365S230060
Reexamination Certificate
active
06747898
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to column decode circuits in memory arrays.
BACKGROUND OF THE INVENTION
Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by specialized programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. A typical Flash memory comprises a memory array, which includes a large number of memory cells. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The data in a cell is determined by the presence or absence of the charge in the floating gate. The cells are usually grouped into sections called “erase blocks”. Each of the cells within an erase block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation, wherein all floating gate memory cells in the erase block are erased in a single operation. For ease of access and management the erase blocks of a non-volatile memory device are typically arranged in “banks” or segments.
Many modern PCs have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a Flash BIOS. Flash memory is also popular in modems because it enables the modern manufacturer to support new protocols as they become standardized.
Both RAM and ROM random access memory devices have memory cells that are typically arranged in an array of rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses. This access mode is referred to as page mode access. To read or write to multiple column locations on a page requires the external application of multiple column addresses. To increase access time, a burst mode access has been implemented. The burst mode uses an internal column address counter circuit to generate additional column addresses. The address counter begins at an externally provided address and advances in response to an external clock signal or a column address strobe signal.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ or 133 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. A modern extended form of SDRAM, that can transfer a data value on the rising and falling edge of the clock signal, is called the double data rate SDRAM (DDR SDRAM, or simply, DDR). SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory. A synchronous Flash memory has been designed that allows for a non-volatile memory device with an SDRAM interface. Although knowledge of the function and internal structure of a synchronous Flash memory is not essential to understanding the present invention, a detailed discussion is included in U.S. patent application Ser. No. 09/627,682 filed Jul. 28, 2000 and titled, “Synchronous Flash Memory,” which is commonly assigned and incorporated by reference.
FIG. 1
shows a simplified diagram of a system
128
incorporating a Flash memory
100
of the prior art coupled to a processing device or controller
102
. The Flash memory
100
has an address interface
104
, a control interface
106
, and a data interface
108
that are each coupled to the processing device
102
to allow memory read and write accesses. Internally to the Flash memory device a control state machine
110
directs internal operation of the Flash memory device; managing the Flash memory array
112
and updating RAM control registers and non-volatile erase block management registers
114
. The RAM control registers and tables
114
are utilized by the control state machine
110
during operation of the Flash memory
100
. The Flash memory array
112
contains a sequence of memory banks or segments
116
. Each bank
116
is organized logically into a series of erase blocks (not shown). Memory access addresses are received on the address interface
104
of the Flash memory
100
and divided into a row and column address portions. On a read access the row address is latched and decoded by row decode circuit
120
, which selects and activates a row page (not shown) of memory cells across a selected memory bank. The bit values encoded in the output of the selected row of memory cells are coupled from a local bitline (not shown) to a global bitline (not shown) and detected by sense amplifiers
122
associated with the memory bank. The column address of the access is latched and decoded by the column decode circuit
124
. The output of the column decode circuit selects the desired column data from the sense amplifier outputs and coupled to the data buffer
126
for transfer from the memory device through the data interface
108
. On a write access the row decode circuit
120
selects the row page and column decode circuit selects write sense amplifiers
122
. Data values to be written are coupled from the data buffer
126
to the write sense amplifiers
122
selected by the column decode circuit
124
and written to the selected floating gate memory cells (not shown) of the memory array
112
. The written cells are then reselected by the row and column decode circuits
120
,
124
and sense amplifiers
122
so that they can be read to verify that the correct values have been programmed into the selected memory cells.
Sense amplifiers of modern memory devices are typically incorporated internal to the memory arrays. Many modern memory architectures with dense memory arrays save on scarce circuit and routing resources by not fully decoding the column address before it is routed into the array proper, minimizing the number of column select lines and circuit resources they utilize routing through the array. Once the partially decoded column select lines are routed to the sense amplifiers in the interior of the memory array, the remainder of the column address is decoded to select the appropriate read and write sense amplifiers. Typically this decoding is accomplished by a series coupled sequence of pass transistors which selectively enable to pass the output of the desired sense amplifiers.
This partial decoding approach avoids the circuit and routing resource expense of a fully decoded column address approach. However, the partial decoding approach increases the number of “logic levels” of the resulting column decoder circuit,
Leffert Jay & Polglaze P.A.
Mai Son
Micro)n Technology, Inc.
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