Static information storage and retrieval – Hardware for storage elements
Reexamination Certificate
2007-12-27
2010-10-05
Phan, Trong (Department: 2827)
Static information storage and retrieval
Hardware for storage elements
C365S189050, C365S189080, C365S230080, C365S233100, C365S233110, C365S233160, C365S233170, C365S233180
Reexamination Certificate
active
07808805
ABSTRACT:
A column address control circuit comprises a control unit for outputting a control signal in response to a DDR mode signal and a first signal, and an address counting unit configured to receive a start column address and output a start column address in response to the control signal. The first signal is a burst read single write mode signal. The control signal is activated when the first signal is activated in a DDR mode. The control unit includes a first logic unit for performing an AND operation of the DDR mode signal and the first signal, and a second logic unit for performing an OR operation of an output signal of the first logic unit and a SDR mode signal.
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Cooper & Dunham LLP
Hynix / Semiconductor Inc.
Phan Trong
White John P.
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