Column address buffering circuit

Details Column address buffering circuit Column address buffering circuit

2001-12-26

2003-04-01

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S233100, C365S233500, C365S233100

Reexamination Certificate

active

06542433

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a peripheral circuit for use with a synchronous semiconductor memory device and, more particularly, to a column address buffering circuit.
BACKGROUND
A double data rate synchronous dynamic random access memory (DDR SDRAM), which is recently emerging as a very high speed memory device, is an SDRAM in which data or instructions are inputted or outputted in synchronization with falling edges and rising edges of a clock signal. For instance, it is possible to obtain data corresponding to a clock signal of 200 megahertz (MHz) using both the rising and falling edges of a 100 MHz clock signal.
Like a conventional SDRAM, the DDR SDRAM performs a column access operation by using an internal clock signal aligned to rising edges of an external clock signal. To execute the column access operation synchronized to the rising edges and the falling edges of the external clock signal, the DDR SDRAM should employ a 2-bit prefetch scheme in which an access operation for rising data and falling data is performed in one clock cycle.
For example, if a column address ‘(A2, A1, A0)=(0, 0, 0)’ is inputted when a burst length is 2 and a burst type is a sequential type, although, on the outside, it looks like data corresponding to addresses of (0, 0, 1), (0, 1, 0) and (0, 1, 1) are sequentially outputted, internally, access operations for the column addresses of (0, 0, 0) and (0, 0, 1) are simultaneously performed in one clock cycle and those for the column addresses of (0, 1, 0) and (0, 1, 1) are simultaneously executed in the next clock cycle.
Herein, the ‘burst length’ means a length of data continuously outputted from a clock synchronous memory device such as an SDRAM.
As described above, when the burst length is 2, two column addresses are internally processed as aligned to the external clock signal. Therefore, if a column address A
1
is constant regardless of a least significant column address A
0
having a logic low or a logic high state, the memory is merely required to internally process a most significant column address to the lower column address A
1
regardless of the state of the least significant column address A
0
.
However, if a logic state of the column address A
1
is differently generated according to the logic state of the least significant column address A
0
, internally, the column address A
1
is processed differently according to the logic state of the least significant column address A
0
. For instance, if column addresses (A
1
, A
0
) are (0, 0), internal column addresses to be processed in a corresponding clock are (0, 0) and (0, 1). Further, if column addresses (A
1
, A
0
) are (1, 0), internal column addresses to be processed in the corresponding clock become (1, 0) and (1, 1). Therefore, in case the least significant column address A
0
has a logic low state, its upper column address A
1
is processed regardless of the logic state of the least significant column address A
0
.
However, if starting column addresses (A
1
, A
0
) are (0, 1) or (1, 1), column addresses to be simultaneously processed in a corresponding clock become (1, 0) and (0, 0) and the column address A
1
should be internally inverted. That is, in case the least significant bit address A
0
has a logic high state, an inverted column address of A
1
, which is generated through a separate process, should be used.
In general, for the 2-bit prefetch scheme, it is common to classify cells in a bank in a memory device into odd and even cells and to access the odd cells and the even cells separately. Therefore, the column address A
1
of the odd cell is generated to have a logic state identical to that of an external input address signal while the column address A
1
of the even cell is produced to have a logic state varying depending on a logic state of the least significant column address A
0
.
Referring to
FIG. 1
, a block diagram of a conventional column address buffering circuit is shown. The column address buffering circuit comprises a multiplicity of address buffers
10
,
12
,
14
, a plurality of address latches
20
,
22
,
24
and a bit transition detecting unit
30
for detecting logic states of lower column addresses corresponding to a burst length and outputting address signals at
1
_od and at
1
_ev to access an odd cell and an even cell.
Referring to
FIG. 2
, a circuit diagram of the bit transition detecting unit
30
in
FIG. 1
when the burst length is 2 is illustrated. The bit transition detecting unit
30
includes a control signal generating block
31
for producing control signals set and setb. The control signal generating block
31
includes a 3-input NAND gate NAND
1
that receives an output signal at_col_
0
of the address latch
20
(
FIG. 1
) and inverted signals of an input signal A generated according to the burst length and an input signal B produced according to a burst type (e.g., a sequential or an interleave type) and generates the control signal set and an inverter IN
6
inverting the control signal set to thereby produce the inverted control signal setb.
The bit transition detecting unit
30
further includes an output block
32
for providing its following predecoder (not shown) with the address signals at
1
_od and at
1
_ev in response to the control signals set and setb. The output block
32
includes an inverter chain IN
1
and IN
2
for buffering the output signal at_col_
1
of the address latch
20
to thereby output a column address signal at
1
_od for an odd cell. The output block
32
also includes two switching components MT
1
and MT
2
for selectively providing a following predecoder (not shown) with the output signal at_col_
1
or an inverted signal of the output signal at_ col_
1
as a column address signal at
1
_ev for an even cell in response to the control signals set and setb.
Hereinafter, the operation of the above column address buffering circuit will be described with reference to
FIGS. 1 and 2
.
First of all, the address buffers
10
,
12
,
14
receive and buffer a plurality of column addresses A
0
, A
1
, An, respectively, in response to an internal clock signal clkp
4
and the address latches
20
,
22
,
24
receive signals out_
0
, out_
1
, out_n provided from the address buffers
10
,
12
,
14
, respectively, and generate output signals at_col_
0
, at_col_
1
, at_col_n responsive to an enabled address strobe signal add_stb.
The bit transition detecting unit
30
is provided with the lower bit address signals, e.g., at_col_
0
and at_col_
1
when the burst length BL is 2, applicable to the burst length among the output signals at_col_
0
, at_col_
1
, at_col_n of the address latches
20
,
22
,
24
, and determines whether or not inverting an upper bit address signal, e.g., A
1
when BL is 2, according to a logic state of the lower bit address signal, e.g., A
0
when BL is 2, thereby transferring output address signals at
1
_ev and at
1
_od to the following predecoder (not shown).
Referring to
FIG. 3
, there is provided an operational timing diagram of the address buffering circuit in FIG.
1
. In
FIG. 3
, if column addresses A
0
and A
1
having the waveform of (a) and (b) are inputted, two signals out_
0
and out_
1
having the waveform of (d) and (e) are simultaneously generated in synchronization with a rising edge of an internally generated clock signal clkp
4
having the waveform of (c).
Subsequently, if there is coupled an address strobe signal add_stb having the waveform of (f), which is a kind of internal clock control signals, the internal signals, e.g., at_col_
2
, at col_n, except the lower bit signals at_col_
0
and at_col_
1
corresponding to the burst length are generated in synchronization with the address strobe signal add_stb while the internal signals at
1
_ev and at
1
_od corresponding to the even cell and the odd cell, respectively, are outputted to have the waveform of (h) after being delayed for a certain delay time td by the bit transition detecting unit
30
.
Meanwhile, an access time of data corresponding to the inputted column address is determined by the latest si

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