Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1997-10-23
2001-05-15
Garber, Wendy R. (Department: 2612)
Television
Camera, system and detail
Solid-state image sensor
C348S303000, C348S304000, C348S272000
Reexamination Certificate
active
06233013
ABSTRACT:
INCORPORATION BY REFERENCE
The present specification hereby incorporates by reference the teachings of U.S. Pat. Nos. 5,519,514 and 5,543,838, both assigned to the assignee hereof, as they relate generally to the concepts of integration times and readout routines for photosensors in full-color photosensor arrays.
FIELD OF THE INVENTION
The present invention relates to CMOS active pixel image sensors, also known as depleted-gate photosensors, or simply photogates. More specifically, the present invention relates to a system of transfer circuits by which a plurality of such photogates arranged in parallel can read out signals therefrom, such as in a full-color sensor array.
BACKGROUND OF THE INVENTION
Currently there are two prevalent basic technologies for image sensing with solid-state apparatus, such as in a television camera or document scanner: the charge-coupled device, or CCD, and CMOS. These two technologies have respective practical advantages and disadvantages. Recently, however, there has become available a new sensor technology which is intended to preserve the advantages of either CCDs or CMOS. This technology is known as “CMOS active pixel image sensors” or “depleted-gate photosensors,” or most simply “photogates.” In brief, a small single-stage CCD is fabricated for each photosensor, and the output of the single CCD stage is integrated with CMOS circuitry, such as a transfer circuit. The basic technology of constructing such photogates is disclosed in Mendis, Kemeny, and Fossum, “CMOS Active Pixel Image Sensor,” IEEE Transactions on Electron Devices, Volume 41, No. 3, March 1994.
The basic structure of a photogate-based photosensor is as follows. There is disposed in a silicon structure one doped area with an exposed surface, known as a photogate, which accepts light thereon. When the photogate is exposed to light, a charge is created in the depletion layer thereof. A transfer gate is disposed next to the photogate. When it is desired to transfer the charge from the photogate, a potential is applied to the transfer gate, thus deepening the potential well there. This deepening of the potential well in the transfer gate causes the charge in the photogate to spill into the transfer gate, according to the basic CCD method. This CCD-type charge transfer occurs only once in the process, and the charge spilled into the transfer gate is converted into a voltage with associated CMOS circuitry.
Although photogates have numerous advantages, such as small size, CMOS-compatibility and relative ease of fabrication, certain problems must still be addressed in order to incorporate this technology in, for example, a full-color document scanner. In one type of full-color document scanner, there are provided three separate linear arrays, each array incorporating a relatively large number of photosensors. Each separate linear array of photosensors is filtered with one primary color filter, such as red, blue, and green. The three primary-color-filter linear arrays are then exposed to an original document moving past, to record video signals based on the exposed document. Because each individual linear array is filtered with one primary color, the ultimate output is three color separations based on the original image. One basic problem with using photogate technology as photosensors in this context is that, with currently-known designs of photogates, the integration time of each photogate, which is analogous to the shutter exposure time in a camera, is not readily controllable for individual pixels.
This lack of direct control my cause problems with accurate recording of individual color separations with the arrays of photogates.
DESCRIPTION OF THE PRIOR ART
In the prior art, the article “CMOS Active Pixel Image Sensor,” referenced above, sets forth the basic operating principle of photogates.
U.S. Pat. No. 5,471,515 discloses a monolithic CMOS integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate, a readout circuit including at least an output field effects transistor, and a charge couple device adjacent the photogate. Each photogate has associated therewith at least one charge coupled device stage for transferring charge from the underlying portion of a substrate to a sensing node.
U.S. Pat. No. 5,519,514 discloses a CMOS-type color input scanning array in which there are provided three linear arrays of photosensors, each linear array of photosensors being filtered to be sensitive to one primary color. With each scan cycle of the linear arrays, the exposure period (i.e., integration time) of the photosensors in each array is precisely timed so that the optical “center of gravity” for each exposed area in the original image is superimposed for all of the primary color photosensors.
U.S. Pat. No. 5,543,838 discloses a signal multiplexing system for a color CMOS-type document scanner, in which for each pixel “cell” across the array, three photosensors, each photosensor being filtered to be sensitive to one primary color, are connected through a plurality of transfer circuits to a common node. For each of the three photosensors in the array, a transfer circuit controls the integration time for each photosensor, while another set of transfer circuits carries out the multiplexing through the common node.
U.S. Pat. No. 5,576,763 discloses an active pixel sensor comprising a photosite for generating and storing charge carriers, a transfer transistor and output and reset electronics. The gate of the transfer transistor and the photogate are defined in a single layer of polysilicon. By virtue of its unique structure, the device can operate without a clock or associated driving circuitry.
U.S. Pat. No. 5,587,596 discloses an active pixel sensor cell wherein a single MOS transistor is formed in a well to perform the functions conventionally performed by a photogate/photodiode, sense transistor and access transistor. Light energy striking the well varies the potential of the well which, in turn, varies the threshold voltage of the transistor. As a result, the current sourced by the transistor is proportional to the received light energy.
U.S. Pat. No. 5,625,210 discloses a photosensor device in which photodiodes are fabricated with CCD process steps and integrated into an active pixel architecture.
U.S. Pat. No. 5,631,704 discloses an active pixel imaging system which generates a differential output signal based on the differences in a viewed image between adjacent detected frames. When a particular pixel sensor is activated it generates a voltage signal corresponding to a previous frame's detected light intensity before the pixel is reset, thereby generating a voltage signal corresponding to a present frame's detected light intensity. Dickinson et al., “A 256×256 CMOS Active Pixel Image Sensor With Motion Detection,” 1995 IEEE International Solid-State Circuits Conference, paper TP 13.5, discloses a similar system.
European Patent Application EP-A2-757390 discloses an active pixel image sensor for full-color images, in which each pixel cell of the array includes two photogates, to receive red and green light respectively, and a CMOS-type photodiode for receiving blue light.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, there is provided a photosensitive apparatus comprising a first photogate and a second photogate. Each photogate creates a charge in response to light impinging thereon, and includes a phototransfer gate associated therewith. A charge in the photogate spills into the associated phototransfer gate in response to an applied potential difference between the photogate and the phototransfer gate. A common node is associated with the first phototransfer gate and the second phototransfer gate, the common node being associated with an output line. A reset gate is disposed on a reset node on the output line, the reset gate being used to selectably apply a predetermined reset potential to the reset node. A clearing gate is disposed on the output line between the common node and the reset nod
Hosier Paul A.
Tandon Jagdish C.
Tewinkle Scott L.
Garber Wendy R.
Hutter R.
White Mitchell
Xerox Corporation
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