Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-04-20
2002-04-30
Chow, Dennis-Doon (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S098000
Reexamination Certificate
active
06380916
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a flat panel display device for displaying an image using digital R, G and B signal, and more particularly to a color adjustment circuit for a liquid crystal display (LCD) capable of displaying the image where the preferring color of red(R), green(G) or B(blue) colors is stressed by an user's color taste.
When image is displayed through display devices, it has tendency to prefer the picture screen that R, G or B color is stressed in an user's color taste. Accordingly, it is desired to display the image where the R color is stressed in case of preferring the R color, the G color is stressed in case of preferring the G color or the B color is stressed in case of preferring the B color in accordance with an user's taste.
In the prior art, the method for adjusting the R, G and B colors adjusts the color of the image displayed in the picture screen to a desirable color by varying the luminance according to the voltage of an backlight.
The color characteristic of a TFT-LCD is determined to the characteristics of the R, G and B data, a backlight and a color filter. A color filter should be used a finished products made by a maker.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a color adjustment circuit in a LCD capable of displaying an image by stressing the preferring color of the R, G and B colors in accordance with an user's taste.
It is an aspect of the present invention to provide a color adjustment circuit in a liquid crystal display, comprising: an R data adjusting portion for externally receiving an R data of selected bits, which has a predetermined color level, for adjusting the color level of the received R data to a desirable color level and for generating the color level adjusted-R data; a G data adjusting portion for externally receiving a G data of selected bits, which has a predetermined color level, for adjusting the color level of the received G data to a desirable color level and for generating the color level adjusted-G data; and a B data adjusting portion for externally receiving a B data of selected bits, which has a predetermined color level, for adjusting the color level of the received B data to a desirable color level and for generating the color level adjusted-B data.
The R data adjusting portion includes: a counting portion for counting a first pulse signal to select the desirable color level of the R data and for providing the selected R data and a selection signal; an add/subtraction portion for add/subtracting the received R data and the selected R data from the counting portion in accordance with the first selection signal and for providing an add/subtracted R data and a carry signal; and a data selection portion for selecting the output signal of the add/subtraction portion, a power signal and a ground signal in accordance with the carry signal and the selection signal and for providing the selected signal as the color level-adjusted R data.
The counting portion in the R data adjusting portion includes: a pulse generator for genrating the first pulse signal having a constant period; a switch for setting the desirable color level of the R data; an AND gate for generating a second pulse signal having a phase inverted to the first pulse signal as a clock a signal whenever the switch is pushed; and a counter for counting the clock signal from the AND gate to generate output signals having predetermined bits, a most significant bit being provided as the selection signal and remnant bits being provided as the selected R data to the add/subtraction portion.
The add/subtraction portion in the R data adjusting portion includes; a plurality of exclusive OR gates for carrying out 1's complement to the selected R data from the counting portion; and a plurality of adder/subtracters for receiving the externally received R data and the output signals from the exclusive OR gates, for add/subtracting the received R data and the selected R data in accordance with the selection signal bit by bit and for generating the add/subtracted R data and the carry signal.
The data selection portion in the R data adjusting portion includes a plurality of multiplexers for receiving the respective output signals from the adder/subtraction portion, the power signal and the ground signal and selecting one of them in accordance with the carry signal and the selection signal and for providing the selected one as the color level-adjusted R data.
The G data adjusting portion includes: a counting portion for counting a first pulse signal to select the desirable color level of the G data and for providing the selected G data and a selection signal; an add/subtraction portion for add/subtracting the received G data and the selected G data from the counting portion in accordance with the selection signal and for providing an add/subtracted G data and a carry signal; and a data selection portion for selecting the output signal of the add/subtraction portion, a power signal and a ground signal in accordance with the carry signal and the selection signal and for providing the selected signal as the color level-adjusted G data.
The counting portion in the G data adjusting portion includes: a pulse generator for generating the first pulse signal having a constant period; a switch for setting the desirable color level of the G data; an AND gate for generating a second pulse signal having a phase inverted to the first pulse signal as a clock signal whenever the switch is pushed; and a counter for counting the clock signal from the AND gate to generate output signals having predetermined bits, a most significant bit being provided as the selection signal and remnant bits being provided as the selected G data to the add/subtraction portion.
The add/subtraction portion in the G data adjusting portion includes; a plurality of exclusive OR gates for carrying out 1's complement to the selected G data from the counting portion; and a plurality of adder/subtracters for receiving the externally received G data and the output signals from the exclusive OR gates, for add/subtracting the received G data and the selected G data in accordance with the selection signal bit by bit and for generating the add/subtracted G data and the carry signal.
The data selection portion in the G data adjusting portion includes a plurality of multiplexers for receiving the respective output signals from the adder/subtraction portion, the power signal and the ground signal and selecting one of them in accordance with the carry signal and the selection signal and for providing the selected one as the color level-adjusted G data.
The B data adjusting portion includes: a counting portion for counting a first pulse signal to select the desirable color level of the B data and for providing the selected B data and a selection signal; an add/subtraction portion for add/subtracting the received B data and the selected B data from the counting portion in accordance with the selection signal and for providing an add/subtracted B data and a carry signal; and a data selection portion for selecting the output signal of the add/subtraction portion, a power signal and a ground signal in accordance with the carry signal and the selection signal and for providing the selected signal as the color level-adjusted B data.
The counting portion in the B data adjusting portion includes: a pulse generator for generating the first pulse signal having a constant period; a switch for setting the desirable color level of the B data; an AND gate for generating a second pulse signal having a phase inverted to the first pulse signal as a clock signal whenever the switch is pushed; and a counter for counting the clock signal from the AND gate to generate output signals having predetermined bits, a most significant bit being provided as the selection signal and remnant bits being provided as the selected B data to the add/subtraction portion.
The add/subtraction portion in the B data adjusting portion includes; a plurality of exclusive OR gates for car
Chow Dennis-Doon
Hyundai Display Technology Inc.
Ladas & Parry
Nelson Alecia D.
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