Collective automatic gain control

Details Collective automatic gain control Collective automatic gain control

2003-05-23

2004-04-27

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including gain control means

C330S136000, C330S140000, C455S245100

Reexamination Certificate

active

06727759

ABSTRACT:

TECHNICAL FIELD
The invention relates to automatic gain control in signal receivers.
BACKGROUND
High-speed digital systems such as memory systems sometimes use a form of I/O in which data is defined by a differential voltage signal. A differential voltage signal comprises a pair of complementary signals. A high logic level is represented by setting a first of the signals to a relatively high voltage and the second of the signals to a relatively low voltage. A low logic level is represented by switching the two voltages, so that the first signal has a relatively lower voltage than the second signal. Differential signaling is advantageous because of its relative immunity to noise and other signal degradations. A disadvantage of differential signaling is that it requires two signal lines for every data bit.
In order to reduce the number of data signaling lines, single-ended signaling is often used in high speed circuits. This particular type of signaling is non-differential, although it is sometimes referred to as “pseudo differential” signaling. Pseudo differential signaling specifies logic levels as voltages relative to a common, intermediate reference voltage. For example, a signal might be defined to represent a high logic level whenever its voltage is above the reference voltage, and to represent a low logic level whenever its voltage is below the reference voltage. This type of signaling requires fewer conductors than differential signaling, because a single reference line can be used in conjunction with many data signal lines. Although this type of signaling is less immune to signal degradation than differential signaling, it represents a distinct improvement over signaling systems in which signal levels are specified in terms of absolute voltages, rather than in relation to a specified reference voltage. Typically, a reference voltage signal is transmitted alongside data signals so that the same sources of noise will affect both the reference signal and the data signals. This tends to cancel the effects of the noise and provides some degree of noise immunity.
Regardless of whether signals are differential or non-differential, it is frequently desirable to perform some sort of signal buffering and/or conditioning at the receiving device. This is typically accomplished by a data receiver corresponding to each incoming signal line.
FIG. 1
shows a data receiver
10
that buffers an incoming data signal D
IN
to form a buffered or amplified internal data signal D
OUT
. This circuit uses automatic gain control to achieve a desired voltage amplitude at D
OUT
.
Data receiver
10
comprises a variable gain amplifier
12
that receives D
IN
and produces D
OUT
. The receiver also has an envelope detector
14
that detects the voltage amplitude of signal D
OUT
. An envelope detector or peak detector is a well-known type of circuit whose output voltage tracks the peak or swing voltages of a modulating input voltage such as a data signal.
FIG. 2
shows a simplified example of an envelope detector
14
, comprising an FET control transistor M, a tracking capacitance C, a charging current source I
CH
, and a discharging current source I
DIS
. Transistor M is controlled by data signal D
OUT
to charge capacitance C whenever D
OUT
is relatively high. When the voltage V
ENV
on capacitance C approaches the voltage of D
OUT
, the transistor shuts off because of the reduced gate-to-source voltage of the transistor in this condition. Thus, the transistor charges capacitance C to approximately the “high” logic level of D
OUT
. The size of current source I
CH
determines the “attack” rate of the envelope detector—the rate at which output voltage V
ENV
will climb in response to an increased voltage at D
OUT
. Current source I
DIS
is connected to slowly discharge capacitance C, to account for situations in which the peak levels of D
IN
decrease over time. The size of current source I
DIS
determines the “decay” rate of the envelope detector—the rate at which output voltage V
ENV
will fall in response to a decreased input voltage D
OUT
. I
DIS
is chosen to be small enough so that the voltage at D
OUT
will remain close to its peak value between peaks that occur in D
IN
.
If appropriate sizes are selected for current sources I
CH
and I
DIS
, an envelope detector can be configured to produce an output that closely tracks the peak voltages of a data signal. Although the envelope detector of
FIG. 2
is configured to detect positive signal peaks, the circuit can be easily altered to detect negative peaks in an input signal.
Referring again to
FIG. 1
, envelope detector
14
is configured to determine and track the peak voltage of output signal D
OUT
, and to produce a voltage signal V
ENV
representing this peak voltage. A feedback component
20
receives V
ENV
and compares it to a supplied reference amplitude V
AMP
. The output of feedback component
20
is connected to the gain control of amplifier
12
, forming a feedback loop that operates to minimize any difference between the peak output V
ENV
of signal D
OUT
and the supplied amplitude reference V
AMP
. In other words, this circuit sets the gain of amplifier
12
so that the peak voltage of output D
OUT
is approximately equal to the voltage of V
AMP
. In implementation, feedback component
20
is a g
m
stage whose output increases or decreases depending on the relative values of its inputs.
FIG. 3
shows data receiver
10
, with the generic representation of amplifier
12
of
FIG. 1
being replaced by a more detailed implementation of a differential amplifier circuit. Such a differential amplifier is typically used in conjunction with an input an input data signal D
IN
that is specified relative to an intermediate reference voltage V
REF
, which is relatively constant. The differential amplifier produces a differential voltage output D
OUT
having + and − outputs.
The differential amplifier comprises a differential pair of FET transistors M
2
and M
3
, whose sources are connected in common. The drains of M
2
and M
3
form the high and low outputs of differential voltage output signal D
OUT
, and are connected through respective loads R
1
LOAD
and R
2
LOAD
to a high supply voltage V
dd
. The gates of M
2
and M
3
are connected respectively to D
IN
and V
REF
. The sources of M
2
and M
3
are connected in common through a biasing current source I
BIAS
to a low supply voltage V
ss
.
The input of envelope detector
14
is connected to the positive side of differential output D
OUT
. The output of feedback component
20
controls current source I
BIAS
, which in turn controls the gain of the amplifier circuit. Feedback component
20
receives the output of envelope detector
14
and the amplitude reference V
AMP
, and therefore establishes the gain of the amplifier circuit so that the peak voltage of output signal D
OUT
is approximately equal to V
AMP
.
The circuits described above have been used with success in many situations. However, problems arise in certain situations. One problem arises from the use of automatic gain control and envelope detectors in situations where there are relatively long periods without a transition in the received data signal. For example, a relatively long period in which a data signal remains low results in a decaying envelope voltage, which in turn causes automatic gain control circuits to inappropriately increase circuit gains. Furthermore, in many cases it is challenging to determine the optimal amplitude of D
OUT
. It is desirable to keep the amplitude as low as possible to reduce power consumption, but also to keep it as high as necessary to ensure accurate differentiation between high and low signals.
A further concern arises where a data signal is precisely timed relative to other signals. In cases such as this, it is important to maintain the relative timing between the two or more signals. However, variations in amplification can affect this timing. This problem arises, for example, with incoming signals that must exceed a certain threshold voltage in order for them to be res

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