Semiconductor device manufacturing: process – Including control responsive to sensed condition
Patent
1996-12-20
1999-07-27
Bueker, Richard
Semiconductor device manufacturing: process
Including control responsive to sensed condition
438 9, 438714, 438723, 438733, 438738, 438740, 438743, H01L 2100
Patent
active
059305851
ABSTRACT:
In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. The storage capacitor is formed in a trench etch in a silicon substrate which is partially filled with polysilicon. The substrate is conformally coated by a TEOS SiO.sub.2 collar layer having a non-uniform thickness. A chemistry having a high TEOS SiO.sub.2 /Si3N.sub.4 and polysilicon selectively (i.e. which etches TEOS SiO.sub.2 faster than Si.sub.3 N.sub.4 and polysilicon by a factor of at least 6) is used to anisotropically etch the collar layer. C.sub.4 F.sub.8 /Ar/C) mixtures which have selectivities of 9:1 and 15:1 are adequate. When the surface of the Si.sub.3 N.sub.4 pad layer is reached (this can be accurately detected), the etch is continued a short period of time to ensure the complete removal of the horizontal portions of the collar layer, including at the trench bottom, but not the vertical portions in the trench sidewalls.
REFERENCES:
patent: 4668338 (1987-05-01), Maydan et al.
patent: 4966870 (1990-10-01), Barber et al.
patent: 5286344 (1994-02-01), Blalock et al.
patent: 5312518 (1994-05-01), Kadomura
patent: 5356515 (1994-10-01), Tahara et al.
patent: 5366590 (1994-11-01), Kadomura
patent: 5423945 (1995-06-01), Marks et al.
patent: 5433823 (1995-07-01), Cain
patent: 5445712 (1995-08-01), Yanagida
patent: 5503901 (1996-04-01), Sakai et al.
patent: 5505816 (1996-04-01), Barnes et al.
patent: 5549784 (1996-08-01), Carmody et al.
patent: 5562801 (1996-10-01), Nulty
patent: 5595627 (1997-01-01), Inazawa et al.
patent: 5626716 (1997-05-01), Bosch et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5650339 (1997-07-01), Saito et al.
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5739573 (1998-04-01), Kawaguchi
patent: 5770098 (1998-06-01), Araki et al.
Lee, H.-J., et al "Selective SiO2/Si3N4 etching in magnetized inductively coupled C4F8 plasma" J. Vac. Sci. Technol. B 16(2) pp. 500-506, Mar. 1998.
Coronel Phillipe
MacCagnan Renzo
Bueker Richard
International Business Machines - Corporation
Walsh Robert A.
LandOfFree
Collar etch method to improve polysilicon strap integrity in DRA does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Collar etch method to improve polysilicon strap integrity in DRA, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Collar etch method to improve polysilicon strap integrity in DRA will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-891240