Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Redundant
Reexamination Certificate
2003-06-17
2004-09-21
Nguyen, Long (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Redundant
C327S112000, C327S391000, C326S013000, C326S087000
Reexamination Certificate
active
06794925
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a cold spare redundant circuit capable of providing the desired output if the active circuit becomes unreliable.
BACKGROUND OF THE INVENTION
Many circuit applications require the need for redundancy in which a particular function is provided using redundant circuits such that, if one of circuits fails to provide the desired function, at least one of the other redundant circuits can take over to provide that function.
Redundant circuits may operate in either an active mode or a standby mode. In the active mode, all of the redundant circuits are active and operate in parallel such that, if one of the redundant circuits fails, one or more identical paths exist to continue the function being provided. Also, plural redundant circuits can be operated in the active mode such that a vote is taken of their outputs and the output that is in the majority is used to provide the desired function.
In the standby mode, one of the redundant circuits is active to provide the desired function, but the other redundant circuits are on standby. That is, the outputs of the redundant circuits on standby are not used for any purpose. When the active circuit fails, one of the other redundant circuits is made active. The redundant circuits on standby are either hot spare circuits or cold spare circuits. Hot spare circuits are redundant circuits that are powered up but that are not switched to the output. Cold spare circuits are redundant circuits that are not powered up and provide no signal to the output.
In the case of cold spare redundant circuits, the outputs of the cold spare redundant circuits are frequently tied to the output of the active circuit. Therefore, the cold spare redundant circuits could conceivably electrically interfere with the active circuit.
The present invention is directed to a cold spare circuit that does not electrically interfere with the active circuit.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a redundant system having an output comprises first, second, third, and fourth transistors and first and second control circuits. The first transistor has a gate, a source, and a drain, and the gate of the first transistor is controlled by a function of a first chip. The second transistor has a gate, a source, and a drain, and the source and drain of the first transistor and the source and drain of the second transistor are connected in series between the output and a first potential terminal. The third transistor has a gate, a source, and a drain, and the gate of the third transistor is controlled by a function of a second chip. The fourth transistor has a gate, a source, and a drain, and the source and drain of the third transistor and the source and drain of the fourth transistor are connected in series between the output and a second potential terminal. The first control circuit is connected to the gate of the second transistor and the second control circuit is connected to the gate of the fourth transistor so as to turn on one of the second and fourth transistors at a time.
According to another aspect of the present invention, a method is provided to control first and second cold spare circuits. The first cold spare circuit comprises first and second transistors. The first transistor has a gate, a source, and a drain, and the gate of the first transistor is controlled by a function of a first chip. The second transistor has a gate, a source, and a drain, and the source and drain of the first transistor and the source and drain of the second transistor are connected in series between an output and a first potential terminal. The second cold spare circuit comprises third and fourth transistors. The third transistor has a gate, a source, and a drain, and the gate of the third transistor is controlled by a function of a second chip that is redundant of the first chip. The fourth transistor has a gate, a source, and a drain, and the source and drain of the third transistor and the source and drain of the fourth transistor are connected in series between the output and a second potential terminal. The method comprises the following: controlling the second and fourth transistors so that only one of the first and second transistors is on at a time; providing a non-zero potential to one of the first and second potential terminals corresponding to the one of the second and fourth transistors that is on; and, providing a zero potential to the other of the first and second potential terminals corresponding to the one of the second and fourth transistors that is off.
According to still another aspect of the present invention, a method is provided to control a cold spare circuit. The cold spare circuit comprises first and second transistors. The first transistor has a gate, a source, and a drain, and the gate of the first transistor is controlled by a function of a redundant chip. The second transistor has a gate, a source, and a drain, and the source and drain of the first transistor and the source and drain of the second transistor are connected in series between an output and a potential terminal. The method comprises the following: controlling the second transistor so that the cold spare circuit is on or off; providing a non-zero potential to the potential terminal when the cold spare circuit is controlled to be on; and, providing a zero potential to the potential terminal when the cold spare circuit is controlled to be off.
REFERENCES:
patent: 6272577 (2001-08-01), Leung et al.
patent: 6320433 (2001-11-01), Hinterscher
patent: 6392440 (2002-05-01), Nebel
Honeywell International , Inc.
Nguyen Long
Schiff & Hardin LLP
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